Hi Claudio, > My goal is to have data actually transferred on the bus. So, I think it's just > CPU's cache that I want to disable for my data. Then you'll need to use a memory barrier, as well as use volatile. > Does the volatile command ensure that data is not cached on cpu's cache ? No. The volatile qualifier ensures that the data read access is read from the bus (which may be provided from the L1, L2, or L3 cache), and not optimized away. And that a data write access is actually written to the bus (which may idle pending in the L1, L2 or L3 cache a while until flushed), and not optimized away. I *wish* the volatile qualifier (or some other new keyword) ensures that the data read/write access bypassed the cache. Also note: one some architectures, hardware I/O memory mapped space is not cached. So on those architectures there is no need for a memory barrier, which flushes / syncs the caches. [I'm glossing over the details with some hand-waving generalizations. Details may vary depending on particular platform architecture.] Also of importance: you'll still need the volatile, to make sure the optimizer doesn't eat your intentions. HTH, --Eljay
