Tim Blechmann wrote:
> i've got the following problem:
> i am using the atomic_ops library to use the cmpxchg8b opcode. the
> specific section for x86 machines looks like this:
>
> __asm__ __volatile__("lock; cmpxchg8b %0; setz %1"
> : "=m"(*addr), "=q"(result)
> : "m"(*addr), "d" (old_val1), "a" (old_val2),
> "c" (new_val1), "b" (new_val2) : "memory");
>
> unfortunately, this doesn't compile, when building as a shared library
> with the -fPIC flag, as the `b` register can't be used.
> so i wrote a workaround:
>
> __asm__ __volatile__("push %%ebx; movl %6,%%ebx; lock; cmpxchg8b %0; setz %1; pop %%ebx"
> : "=m"(*addr), "=q"(result)
> : "m"(*addr), "d" (old_val1), "a" (old_val2),
> "c" (new_val1), "m" (new_val2) : "memory");
>
> this piece of code works fine if the -fPIC flag is enabled. but when
> compiling this without -fPIC and switching on optimization (-O), the
> code compiles, but doesn't work correctly anymore. without optimization
> it works fine, though.
>
> is this a compiler bug or a user bug?
Can't you just use the builtin and let gcc worry about it?
result = __sync_bool_compare_and_swap (*addr, old_val, new_val);
http://gcc.gnu.org/onlinedocs/gcc/Atomic-Builtins.html#index-g_t_005f_005fsync_005fbool_005fcompare_005fand_005fswap-2118
Brian
