Hi, I want to do some static analysis of MIPS assembler programs generated by GCC (4.1.1). To simplify this, I do not want to care about (branch) delay slots. I'm only interested in the sequence of executed instructions. My first attempt to get rid of instructions in delay slots was to reorder them. However, this can become quite complicated if there are dependencies between the registers. Here's an example: beq $2,$0,$L12 slt $2,$6,$4 Simply swapping both instructions is obviously not correct. To cut a long story short, is there a way to force GCC to always put nops in the delay slots while using all (other) optimizations enable by -O2? Thanks a lot! Regards, Tobias
