On 1/26/06, Peng Yu wrote:
> Suppose I have a file "main.cc", if I run the following command "g++
> -MM main.cc, I end up with following rule "main.o: main.cc main.h".
>
> What if I want something like the following contents?
> ####################
> main-g.o: main.cc main.h
> $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -g -c -o $@ $<
>
> main-o.o: main.cc main.h
> $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -O3 -c -o $@ $<
> ####################
Hi.
This is not GCC question, but MAKE question ( GNU-MAKE ).
You don't need to write these lines, MAKE performs the calls automatically.
You only change the CXXFLAGS (and etc.) variables, depending on what
compiling options you want.
Example for makefile:
--------------------------------------------- Makefile:
If ($(debug_mode),on)
CXXFLAGS := $(TARGET_ARCH) -g
else
....
end
include gcc_generated_dependencies.make
-------------------------------------------------
gcc_generated_dependencies.make:
# these lines generated with g++
main.o : main.c main.h
-------------------------------------------------
I don't sure I use the correct MAKE syntax. Please read it's docs.
Regards,
Dima.
