Note, I work for, but don't officially speak for AMD. And as a fairly new employee, I won't claim to know the architecture backwards and forwards. So take this as a personal message. Note all of the Linux 64-bit distributions only ship one set of binaries, so the code generated by the compilers is the same. There is at least one instruction (cmpxcg16) that Intel has that AMD doesn't, but the compiler doesn't generate it. In terms of signaling vs quiet Nan, this has been part of the x86 architecture ever since the 80387 chipset provided floating point. I definitely remember reading about it in the 80386 manual. -- Michael Meissner AMD, MS 83-29 90 Central Street Boxborough, MA 01719 -----Original Message----- From: gcc-help-owner@xxxxxxxxxxx [mailto:gcc-help-owner@xxxxxxxxxxx] On Behalf Of Nelson H. F. Beebe Sent: Monday, October 24, 2005 9:22 AM To: Shailesh Birari Cc: beebe@xxxxxxxxxxxxx; gcc-help@xxxxxxxxxxx Subject: Re: Binary compatibility - Xeon & Opteron Shailesh Birari <birarish@xxxxxxxxx> asks on Mon, 24 Oct 2005 02:48:29 -0700 (PDT) whether binaries compiled on AMD64 Opteron will work on EM64T Xeon and vice versa. For about two years, I have been building code on AMD64 Opteron systems with GNU gcc and Intel icc compilers, the latter in the version for the Intel EM64T architecture. The binaries from icc work flawlessly on AMD64. Although the Intel EM64T architecture manuals (680+ pages) make no mention whatever of AMD, it appears that the two architectures are largely, if not completely, binary compatible. Several third-party vendors now ship servers with the Intel Xeon MP processor, which implements EM64T: see http://www.intel.com/products/processor/xeon/procbrief.htm See also http://www.intel.com/products/processor_number/proc_info_table062705.pdf for a list of processors that include EM64T support: Pentium D, Pentium Extreme Edition, upper members of Pentium 4 series, and some members of the Celeron D seris. This is really confusing! After study of the architecture manuals for EM64T and AMD64, I found one area where there may be a difference. Unlike the traditional IA-32 (aka x86) architecture, AMD64 supports two kinds of NaNs: quiet and signaling. The IA-32 floating-point architecture was designed about 1980, five years before the ANSI/IEEE 754-1985 Standard for Binary Floating-Point Arithmetic was finalized. IA-32 offers only quiet NaNs, and their sign is negative, rather than positive. However, this morning I find that the latest Intel IA-32 architecture manual now defines both kinds of NaNs. See p. 4-18 (sequential page 106) of ftp://download.intel.com/design/Pentium4/manuals/25366517.pdf >> ... >> The IA-32 architecture defines two classes of NaNs: quiet NaNs (QNaNs) >> and signaling NaNs (SNaNs). A QNaN is a NaN with the most significant >> fraction bit set; an SNaN is a NaN with the most significant fraction >> bit clear. QNaNs are allowed to propagate through most arithmetic >> operations without signaling an exception. SNaNs generally signal a >> floating-point invalidoperation exception whenever they appear as >> operands in arithmetic operations. >> ... My suspicion is that this may apply only to those IA-32 processor models that have been extended for EM64T support. Perhaps some list readers who have access to real EM64T hardware can confirm by software experiments whether two kinds of NaNs are now supported by Intel. ------------------------------------------------------------------------ ------- - Nelson H. F. Beebe Tel: +1 801 581 5254 - - University of Utah FAX: +1 801 581 4148 - - Department of Mathematics, 110 LCB Internet e-mail: beebe@xxxxxxxxxxxxx - - 155 S 1400 E RM 233 beebe@xxxxxxx beebe@xxxxxxxxxxxx - - Salt Lake City, UT 84112-0090, USA URL: http://www.math.utah.edu/~beebe - ------------------------------------------------------------------------ -------
