Hello, I take the example of SPARC. Each interrupt is associated with a number and CPU jumps to a particular address on interrupt depending on the number. That address handles the interrupt, i.e, ISR should be at that number. There will be space only for four instructions. In gcc tool-chain, how to write ISR? Is writing the OPCODES to the address corresponding to the interrupt number the only way? Any other smart techniques exist? Please guide me. Thanks Srinivasan __________________________________ Do you Yahoo!? Yahoo! Mail - You care about security. So do we. http://promotions.yahoo.com/new_mail
