Hi All, I work in the development of a reconfigurable processor. Actually, we use gcc 2.95.2 to compile code for the processor core inserting the "extended" instruction set through assembler inlining. Well, I have some question about the effectiveness of gcc to manage long and variable latency instructions and to schedule its appropriately. I know that the machine description cannot be dynamically modified because it is only read at compile time, but I like to know if is possible to dynamically set the the latency and (eventually) the issue-delay for a specific instruction. I would to set these params using or an operands or some refs in the opcode and so extracting its from the mnemonic assembly-inlined. Of course, it needs to provide some filtering step... Is it feasible ??? Do it need a huge amount of time ???
I have also a second question: I have a very long instruction word processor and I have some problems to optimize the code and also to legalize it internally to gcc (actually, I use an external scheduler to reorder and legalize the code, but without register renaming...). Only modifying the multiplicity params, I have several problems... and the code produced is strongly sequential. I see a large degree of reuse in the register allocation that introduce more data dependencies than required. How is possible to say at gcc that exist more than one datapath (with compatibility rules) and to force it more efficiently ??? It needs to describe each operation with a double latency to induce a better usage of the register file ??? Suggestions ???
Alternatively, it exists an open-source scheduler, external to gcc, that provides these features (offering better performances...) ???
Thanks in advance, Claudio
