I am working on porting gcc to a core with the following characteristics: 1. Orthogonal and irregular (as ix86) byte register set 2. Pipelined RISC with blocking loads and no delay slots 3. Can load/store byte/half word/word/double word memory into register(s) 4. Segmented memory
does anybody know/guide/point the reference architecture already ported with similar characteristics.
thanks in advance.
