Hi! Thanx for the answer. In your example, " > .section .text1 > foo: b bar > > .section .text2 > bar: " If we take "b bar" as a 32-bit instruction, then to get the relocation information, of the label "bar", we can calculate the 'bar' value using a 16-bit offset. If so, then it would be a 16-bit relocation. Am I correct in assuming this? > -----Original Message----- > From: Richard Sandiford [mailto:rsandifo@xxxxxxxxxx] > Sent: Friday, 19 December, 2003 20:34 PM > To: gagneet@xxxxxxxxx > Cc: gcc-help@xxxxxxxxxxx; gcc@xxxxxxxxxxx > Subject: Re: ELF instruction for section and branch. > > > "Gagneet Singh" <gagneet@xxxxxxxxx> writes: > > I wish to enquire what is the equivalent for a assembly language > > section in the GCC ELF format? > > I'm not quite sure what you mean here, but... > > > Also, we have a problem of getting the output in ELF format where a > > branch instruction is accessing a label in the second section. > > > > Is this possible? > > It sounds like you're asking about code such as: > > .section .text1 > foo: b bar > > .section .text2 > bar: > > Is that right? If so, then no, this isn't supported. The > assembler can't calculate the branch offset because the > distance between foo and bar isn't known until link time. > And unfortunately, due to an infamous problem with the MIPS > ELF spec, there's no relocation that the assembler can use either. > > (The R_MIPS_PC16 relocation was probably designed for > branches, but the ELF spec says it gives a byte offset, > whereas branch instructions need a word offset.) > > Richard >
