[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #4 from Chitlesh GOORAH <cgoorah@xxxxxxxxxxxx>  2008-10-26 06:27:40 EDT ---
True, but since it's his first package for fedora, I prefer that he adopts some
good practices :)

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