Please do not reply directly to this email. All additional comments should be made in the comments box of this bug report. Summary: Review Request: iverilog - Icarus Verilg is a verilog compiler, simulator. https://bugzilla.redhat.com/bugzilla/show_bug.cgi?id=229657 ------- Additional Comments From cbalint@xxxxxxxxxx 2007-02-26 13:31 EST ------- ping. update ? (pcnet.ro has verilog employee ?!, [*cbalint remark and wonders how an ISP is dealing with verilog ?!, maybe in their free time.]) Yes, sorry for confusions, the new path is: http://openrisc.rdsor.ro/iverilog-20070123-3.src.rpm > Visually seems fine. And yes, since I have a few dozens hardware engineers You review this package visualy, by functionality or by the way how its packed to meet fedora-standards ? > around, I prefer to have one of them test the program. And no, I do not >expect it to replace Questa or VCS yet. What to test ? As i mentioned this is not kind of from today till tomorrow software, look @ http://www.icarus.com/eda/verilog/, you will notice that it was developed over few years, with some obvious efforts by some contributors and in recent time even enhanched by some well known companies like bsemi.com or sun.com And by the way, if a huge project (~1mil gates) prove the functionality as debugger and compiler do you think it can be worse ? 1) http://www.opencores.org/projects.cgi/web/s1_core/overview , yes they use test scripts as alterative to VCS and seems run fine. Still works are in progress over that project (just look inside the project) 2) Olso, mention as contributor to openrisc cpu that iverilog is used inside that project in some cases quite exclusive, and its kinda cpu that was taped even in real silicon, and it iverilog do great job in simulation. 3) We are supposed to review the package not compare verilog compilers or whatever this kind of task, you cannot expect to compet with whatever comercial compilers, so that is task for upstream contributors not for fedora. And by the way debian packed it in their distro since few years. 4) Yes it has problems. There are buch of problems in parser e.g, but basic verilog compile ans simulation is OK, if you know to avoid tham you can avoid in very large projects. But wich opensource project is perfect ? iVerilog meant to be a complementary tool for geda-* tools wich are already in -extras ! And geda cannot replace altium.orcad or comercial software ! If want to review functionality and contribute please look forward for mainstream contributions, (64 arches still have some minor leaks, parser is sucky and so on with the list of TODO), otherwise please consider this as a fedora-extra package wich i request for submission. I am looking forward to push this to -extras for make it aviable for fedora folks. And regarding testcases i am right now looking forward to pack in -5 the testcases that comes as extra package on icarus website. /cristian -- Configure bugmail: https://bugzilla.redhat.com/bugzilla/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the QA contact for the bug, or are watching the QA contact. _______________________________________________ Fedora-package-review mailing list Fedora-package-review@xxxxxxxxxx http://www.redhat.com/mailman/listinfo/fedora-package-review