Alan Cox wrote:
On Tue, May 15, 2007 at 03:28:15PM -0400, William Cohen wrote:
linked programs like SPEC CPU to provide workload for the simulator. This
is very different than the typical shared-library, GUI application
You know you can catch TLB misses on some real x86 processors I assume ?
(You load the page table entry as missing then when you take the trap you
put the entry in, touch the page to load it, and then mark it missing again)
Alan
Hi Alan,
This method would address some of the for future work: how to speed up the data
collection and avoid the distortions caused by the addition mmap regions
valgrind pulls in.
I think that there have been some previous research implementing this, e.g. Tape
Worm. Just thinking how this TLB trap handling would work for the following cases:
instructions spanning pages
instructions with data reference (two (or more) page accesses)
The ability not to need a dedicated machine did factor into the choice. The use
of Valgrind was also influence about what students are comfortable with.
Modifying valgrind, a user-space only tool, is a bit easier when things don't
work correctly for a student.
-Will
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