Per this fesco ticket: https://fedorahosted.org/fesco/ticket/1484#comment:3 I have orphaned all of the packages that had chitlesh as a point of contact: LabPlot -- Data Analysis and Visualization ( master f23 f22 f21 ) alliance -- VLSI EDA System ( el6 el5 ) archimedes -- 2D Quantum Monte Carlo simulator for semiconductor devices ( master f23 f22 f21 el6 el5 ) covered -- Verilog code coverage analyzer ( master f23 f22 f21 el5 ) crystal-clear -- Crystal Clear KDE Icon set ( master f23 f22 f21 ) crystal-project -- Crystal Project KDE Icon set ( master f23 f22 f21 ) dia-CMOS -- Dia CMOS Shapes ( master f23 f22 f21 el6 el5 ) dia-Digital -- Dia Digital IC logic shapes ( master f23 f22 f21 el6 el5 ) dia-electric2 -- Dia Digital IC logic shapes ( master f23 f22 f21 el6 el5 ) dia-electronic -- Dia Digital IC logic shapes ( master f23 f22 f21 el6 el5 ) dinotrace -- Waveform viewer for electronics ( master f23 f22 f21 el6 el5 ) drawtiming -- A command line tool for generating timing diagrams ( master f23 f22 f21 el6 el5 ) eclipse-eclox -- Eclipse-based doxygen plugin ( master f23 f22 f21 el6 el5 ) eclipse-texlipse -- Eclipse plugin for editing Latex ( master f23 f22 f21 el6 el5 ) eclipse-veditor -- Eclipse-based Verilog/VHDL plugin ( master f23 f22 f21 el6 el5 ) electric -- Sophisticated ASIC and MEM CAD System ( master f23 f22 f21 el6 el5 ) electronics-menu -- Electronics Menu for the Desktop ( master f23 f22 f21 epel7 el6 el5 ) emacs-verilog-mode -- Verilog mode for Emacs ( master f23 f22 f21 el6 el5 ) fped -- A footprint editor used by openmoko developers ( master f23 f22 f21 el6 el5 ) freehdl -- GPLed free VHDL ( master f23 f22 f21 el6 el5 ) gds2pov -- GDS2 layout file to POV-Ray conversion ( master f23 f22 f21 el6 el5 ) geda-gaf -- Design Automation toolkit for electronic design ( master f23 f22 f21 el6 el5 ) geda-gnetlist -- Netlister for the gEDA project ( el6 el5 ) gerbv -- Gerber file viewer from the gEDA toolkit ( master f23 f22 f21 el6 el5 ) gnucap -- The Gnu Circuit Analysis Package ( el6 el5 ) gputils -- Development utilities for Microchip (TM) PIC (TM) microcontrollers ( el6 el5 ) gresistor -- Gnome resistor color code calculator ( master f23 f22 f21 el6 el5 ) irsim -- Switch-level simulator used even for VLSI ( master f23 f22 f21 el6 el5 ) iverilog -- Icarus Verilog is a verilog compiler and simulator ( master f23 f22 f21 el6 el5 ) keurocalc -- KEurocalc is a universal currency converter and calculator ( master f23 f22 f21 ) kmenu-gnome -- K Menu with Gnome directory ( master f23 f22 f21 ) knetstats -- A KDE Network monitor ( master f23 f22 f21 ) kpolynome -- A polynome calculation program ( master f23 f22 f21 ) kshutdown -- Graphical shutdown utility for KDE 4 ( master f23 f22 f21 ) ktechlab -- Development and simulation of micro-controllers and electronic circuits ( master f23 f22 f21 el6 el5 ) liborigin -- Library for reading OriginLab OPJ project files ( master f23 f22 f21 el6 el5 ) libstroke -- A stroke interface library ( master f23 f22 f21 el6 el5 ) linsmith -- A Smith charting program ( master f23 f22 f21 el6 el5 ) magic -- A very capable VLSI layout tool ( master f23 f22 f21 el6 el5 ) mot-adms -- An electrical compact device models converter ( master f23 f22 f21 el6 el5 ) netgen -- LVS netlist comparison tool for VLSI ( master f23 f22 f21 el6 el5 ) ngspice -- A mixed level/signal circuit simulator ( master f23 f22 f21 el6 el5 ) ovm -- Open Verification Methodology : IEEE 1800 SystemVerilog standard ( master f23 f22 f21 el6 el5 ) pcb -- An interactive printed circuit board editor ( master f23 f22 f21 el6 el5 ) perl-Hardware-Verilog-Parser -- Complete grammar for parsing Verilog code using perl ( master f23 f22 f21 el6 el5 ) perl-Hardware-Vhdl-Lexer -- Split VHDL code into lexical tokens ( master f23 f22 f21 el6 el5 ) perl-Hardware-Vhdl-Parser -- Complete grammar for parsing VHDL code using perl ( master f23 f22 f21 el6 el5 ) perl-Hardware-Vhdl-Tidy -- VHDL code prettifier ( master f23 f22 f21 el6 el5 ) perl-ModelSim-List -- Analyse the 'list' output of the ModelSim simulator ( master f23 f22 f21 el6 el5 ) perl-Perlilog -- Verilog environment and IP core handling in Perl ( master f23 f22 f21 el5 ) perl-SystemC-Vregs -- Utility routines used by vregs ( master f23 f22 f21 el6 el5 ) perl-SystemPerl -- SystemPerl Perl module ( master f23 f22 f21 el6 el5 ) perl-Verilog-CodeGen -- Verilog code generator ( master f23 f22 f21 el6 el5 ) perl-Verilog-Perl -- Verilog parsing routines ( master f23 f22 f21 el6 el5 ) perl-Verilog-Readmem -- Parse Verilog $readmemh or $readmemb text file ( master f23 f22 f21 el6 el5 ) pharosc -- VLSI and ASIC Technology Standard Cell Libraries ( master f23 f22 f21 el6 el5 ) pikdev -- IDE for development of PICmicro based application (under Linux/KDE) ( master f23 f22 f21 el6 el5 ) piklab -- Development environment for applications based on PIC & dsPIC microcontrollers ( master f23 f22 f21 ) pikloops -- Code generator for PIC delays ( master f23 f22 f21 el6 el5 ) qt-qsa -- QT Script for Applications ( master f23 f22 f21 el6 el5 ) qwtplot3d -- Qt/OpenGL-based C++ library providing a bunch of 3D-widgets ( master f23 f22 f21 el6 ) sk2py -- Migrates Cadence Skill based PCells to Python PyCells ( master f23 f22 f21 el6 el5 ) toped -- VLSI IC Layout Editor ( master f23 f22 f21 el6 el5 ) trac-peerreview-plugin -- Framework for realtime code review within Trac ( master f23 f22 f21 el6 el5 ) vhd2vl -- VHDL to Verilog translator ( master f23 f22 f21 el6 el5 ) wb_builder -- Wishbone Bus Builder ( master f23 f22 f21 el6 el5 ) xcircuit -- Electronic circuit schematic drawing program ( master f23 f22 f21 el6 el5 ) Please consider taking on any that you feel you can maintain for the Fedora project. kevin
Attachment:
pgpPCm6eQTXDV.pgp
Description: OpenPGP digital signature
-- devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxxx https://admin.fedoraproject.org/mailman/listinfo/devel Fedora Code of Conduct: http://fedoraproject.org/code-of-conduct
