Hi Philipp,
On 01/08/2016 12:50 AM, Philipp Zabel wrote:
Hi Yakir,
Am Donnerstag, den 07.01.2016, 18:15 +0800 schrieb Yakir Yang:
Hi Philipp,
Thanks for your fast respond :)
On 01/07/2016 06:04 PM, Philipp Zabel wrote:
Am Donnerstag, den 07.01.2016, 17:02 +0800 schrieb Yakir Yang:
RK3229 integrate an DesignedWare HDMI2.0 controller and an INNO HDMI2.0 phy,
the max output resolution is 4K.
Signed-off-by: Yakir Yang <ykk@xxxxxxxxxxxxxx>
It sounds like the INNO HDMI2.0 phy is not necessarily specific to
RK3229 but might also appear in other SoCs? If so, I think this should
be implemented in a separate phy driver and be used by dw_hdmi-rockchip.
Do you mean I should create a new phy driver that place in "driver/phy"
directly ?
Possibly, yes. The exynos video phys are already there. I have kept the
mediatek dsi/hdmi phys together with the DRM driver, but I suppose I
could move them there, too.
I have think about this idea, and it would make things much clean. But
INNO PHY
driver need the target pixel clock in drm_display_mode, I didn't find a
good way
to pass this variable to separate phy driver. Do you have some idea ?
We'd need to extend the PHY API for this. For the mediatek phys we have
side-stepped the issue by wiring up the PLL output to the common clock
framework.
Wow, I have look at your "drm/mediatek: Add HDMI support" patch, it's
great to
registers a common clock framework.
I expect besides the pixel clock frequency, it might also be necessary
to inform the PHY about cycles per pixel for deep color modes.
INNO PHY didn't need the color depth directly, driver could get the
input pixel
clock rate, and then hdmi core driver could set TMDS rate though common
clock framework.
Anyway it's great material, I would update the new version out.
Thanks a lot
- Yakir
regards
Philipp
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