On Tue, Sep 22, 2015 at 04:54:54PM -0400, Alex Deucher wrote:
> On Tue, Sep 22, 2015 at 4:21 PM, Borislav Petkov <bp@xxxxxxxxx> wrote:
> > Hi Alex,
> >
> > On Tue, Sep 22, 2015 at 03:58:03PM -0400, Alex Deucher wrote:
> >> What system is this?
> >
> > my workstation - an
> >
> > "To be filled by O.E.M. To be filled by O.E.M./M5A97 EVO R2.0, BIOS 1503 01/16/2013"
> >
> > you gotta love the "To be filled" crap. In any case, it is an ASUS M5A97
> > EVO R2.0. RD890 chip AFAICT.
> >
> >> What GPU are you using?
> >
> > RV635. Here's some dmesg:
> >
> > [ 6.489016] [drm] initializing kernel modesetting (RV635 0x1002:0x9598 0x1043:0x01DA).
> > [ 7.509177] radeon 0000:01:00.0: VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF (512M used)
> > [ 7.518010] radeon 0000:01:00.0: GTT: 512M 0x0000000020000000 - 0x000000003FFFFFFF
> > [ 7.525724] [drm] Detected VRAM RAM=512M, BAR=256M
> > [ 7.530608] [drm] RAM width 128bits DDR
> > [ 7.535168] [TTM] Zone kernel: Available graphics memory: 8132226 kiB
> > [ 7.541779] [TTM] Zone dma32: Available graphics memory: 2097152 kiB
> > [ 7.548420] [TTM] Initializing pool allocator
> > [ 7.552896] [TTM] Initializing DMA pool allocator
> > [ 7.558176] [drm] radeon: 512M of VRAM memory ready
> > [ 7.563131] [drm] radeon: 512M of GTT memory ready.
> > [ 7.568151] [drm] Loading RV635 Microcode
> > [ 7.577382] [drm] Internal thermal controller without fan control
> > [ 7.584349] [drm] radeon: power management initialized
> > [ 7.590443] [drm] GART: num cpu pages 131072, num gpu pages 131072
> > [ 7.597266] [drm] enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0
> > [ 7.624386] [drm] PCIE GART of 512M enabled (table at 0x0000000000254000).
> > [ 7.631544] radeon 0000:01:00.0: WB enabled
> > [ 7.635794] radeon 0000:01:00.0: fence driver on ring 0 use gpu addr 0x0000000020000c00 and cpu addr 0xffff880427ef7c00
> > [ 7.647039] radeon 0000:01:00.0: fence driver on ring 5 use gpu addr 0x00000000000521d0 and cpu addr 0xffffc900008121d0
> > [ 7.657924] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
> > [ 7.664601] [drm] Driver supports precise vblank timestamp query.
> > [ 7.670780] radeon 0000:01:00.0: radeon: MSI limited to 32-bit
> > [ 7.676801] radeon 0000:01:00.0: radeon: using MSI.
> > [ 7.681863] [drm] radeon: irq initialized.
> > [ 7.717757] [drm] ring test on 0 succeeded in 0 usecs
> > [ 7.897466] [drm] ring test on 5 succeeded in 1 usecs
> > [ 7.902585] [drm] UVD initialized successfully.
> > [ 7.908108] [drm] ib test on ring 0 succeeded in 0 usecs
> > [ 8.558968] [drm] ib test on ring 5 succeeded
> > [ 8.568734] [drm] Radeon Display Connectors
> > [ 8.573005] [drm] Connector 0:
> > [ 8.576189] [drm] DVI-I-1
> > [ 8.579062] [drm] HPD1
> > [ 8.581657] [drm] DDC: 0x7e50 0x7e50 0x7e54 0x7e54 0x7e58 0x7e58 0x7e5c 0x7e5c
> > [ 8.589172] [drm] Encoders:
> > [ 8.592234] [drm] DFP1: INTERNAL_UNIPHY
> > [ 8.596492] [drm] CRT2: INTERNAL_KLDSCP_DAC2
> > [ 8.601182] [drm] Connector 1:
> > [ 8.604302] [drm] DIN-1
> > [ 8.607012] [drm] Encoders:
> > [ 8.610043] [drm] TV1: INTERNAL_KLDSCP_DAC2
> > [ 8.614642] [drm] Connector 2:
> > [ 8.617760] [drm] DVI-I-2
> > [ 8.620621] [drm] HPD2
> > [ 8.623226] [drm] DDC: 0x7e40 0x7e40 0x7e44 0x7e44 0x7e48 0x7e48 0x7e4c 0x7e4c
> > [ 8.630719] [drm] Encoders:
> > [ 8.633749] [drm] CRT1: INTERNAL_KLDSCP_DAC1
> > [ 8.638436] [drm] DFP2: INTERNAL_KLDSCP_LVTMA
> > [ 8.719815] [drm] fb mappable at 0xC0355000
> > [ 8.724089] [drm] vram apper at 0xC0000000
> > [ 8.728243] [drm] size 9216000
> > [ 8.731371] [drm] fb depth is 24
> > [ 8.734664] [drm] pitch is 7680
> > [ 8.739009] fbcon: radeondrmfb (fb0) is primary device
> > [ 8.802887] Console: switching to colour frame buffer device 240x75
> > [ 8.818487] radeon 0000:01:00.0: fb0: radeondrmfb frame buffer device
> > [ 8.824948] radeon 0000:01:00.0: registered panic notifier
> > [ 8.846452] [drm] Initialized radeon 2.42.0 20080528 for 0000:01:00.0 on minor 0
> >
> >> Can you bisect?
> >
> > It is my workstation so it will take longer but I'll try.
> >
> > If you can think of some particular commits I should try, let me know.
>
> Sorry, I can't think of anything off hand. I suspect it was some
> change or cleanup in the core drm code.
The locking check is new, but I was only adding locking checks, not yet
reworking the locking itself. So the backtrace is likely (but not 100%
guaranteed) a red herring.
Strange thing is that I've tested this on a radeon over here and I don't
see this backtrace ... wut. Below diff should appease the backtraces at
least.
-Daniel
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index d8319dae8358..9f05de73ae97 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1734,9 +1734,11 @@ int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
if (fbcon) {
drm_helper_resume_force_mode(dev);
/* turn on display hw */
+ drm_modeset_lock_all(dev);
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
}
+ drm_modeset_unlock_all(dev);
}
drm_kms_helper_poll_enable(dev);
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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