| Bug ID | 91749 |
|---|---|
| Summary | Tonga IH ring misaligned |
| Product | DRI |
| Version | DRI git |
| Hardware | Other |
| OS | All |
| Status | NEW |
| Severity | normal |
| Priority | medium |
| Component | DRM/AMDgpu |
| Assignee | dri-devel@lists.freedesktop.org |
| Reporter | jay@jcornwall.me |
From amdgpu_ih.c:
adev->irq.ih.ring = kzalloc(adev->irq.ih.ring_size + 8, GFP_KERNEL);
if (adev->irq.ih.ring == NULL)
return -ENOMEM;
adev->irq.ih.rb_dma_addr = pci_map_single(adev->pdev,
(void *)adev->irq.ih.ring,
adev->irq.ih.ring_size,
PCI_DMA_BIDIRECTIONAL);
The Tonga IH_RB_BASE register requires 256B alignment. kzalloc does not
guarantee this, e.g.:
adev->irq.ih.ring: 0xFFFF880835B22148
adev->irq.ih.rb_dma_addr: 0x835B22148
IH_RB_BASE: 0835b221
This causes amdgpu_ih_decode_iv to read ahead of the last written IV, missing
it, when this misalignment occurs.
You are receiving this mail because:
- You are the assignee for the bug.
_______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
