The Nvidia blob allows a pixel clock up to 225 MHz in version 346.59, but only allowed 165MHz in version 295 for HDMI connections. This was tested with a GF114 (Nvidia GTX 560 TI) and a HDMI monitor which used 225 MHz pixel clock and a signal link DVI monitor with a pixel clock of less than 165 MHz. This should also be tested with some other device, but I only have this one graphics card. The HDMI standard <= 1.2 allowed a maximal pixel clock of 165 MHz and the HDMI standard >= 1.3 allows a maximal pixel clock of 340 MHz. One DVI link only allows a maximum clock of 165 MHz, so this should only be changed for HDMI. My assumption is that all Nvidia cards with HDMI support a Pixel clock of 225 MHz, but I haven't tested this Signed-off-by: Hauke Mehrtens <hauke@xxxxxxxxxx> --- drivers/gpu/drm/nouveau/nouveau_connector.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 3162040..9191545b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -815,8 +815,10 @@ get_tmds_link_bandwidth(struct drm_connector *connector) struct nouveau_drm *drm = nouveau_drm(connector->dev); struct dcb_output *dcb = nv_connector->detected_encoder->dcb; - if (dcb->location != DCB_LOC_ON_CHIP || - drm->device.info.chipset >= 0x46) + if (drm_detect_hdmi_monitor(nv_connector->edid)) + return 225000; + else if (dcb->location != DCB_LOC_ON_CHIP || + drm->device.info.chipset >= 0x46) return 165000; else if (drm->device.info.chipset >= 0x40) return 155000; -- 2.1.4 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
