Comment # 21
on bug 89699
from Maxqia
Did some Bisecting and I Got ... 67a77ecdec3ba701eb63783535c43abf6eb1ab29 is the first bad commit commit 67a77ecdec3ba701eb63783535c43abf6eb1ab29 Author: Marek Olšák <marek.olsak@amd.com> Date: Sun Jan 4 22:16:53 2015 +0100 radeonsi: don't use TC L2 for updating descriptors on SI It's causing problems, because we mix uncached CP DMA with cached WRITE_DATA when updating the same memory. The solution for SI is to use uncached access here, because CP DMA doesn't support cached access. CIK will be handled in the next patch. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> :040000 040000 76fed826a37a921280bbb3c30b27921b58a143db 6a5d816cf39df3265bd9a672cecb5ab94ab97195 M src
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