CHV/BSW platform supports various Gamma correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
1. Adds the core function to program Gamma correction values for CHV/BSW
platform
2. Adds Gamma correction macros/defines
Signed-off-by: Shashank Sharma <shashank.sharma@xxxxxxxxx>
Signed-off-by: Kausal Malladi <Kausal.Malladi@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++
drivers/gpu/drm/i915/intel_atomic.c | 6 ++
drivers/gpu/drm/i915/intel_color_manager.c | 154 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_color_manager.h | 12 +++
drivers/gpu/drm/i915/intel_drv.h | 2 +
5 files changed, 184 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 313b1f9..36672e7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7900,4 +7900,14 @@ enum skl_disp_power_wells {
#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
+/* Color Management */
+#define PIPEA_CGM_CONTROL (VLV_DISPLAY_BASE + 0x67A00)
+#define PIPEA_CGM_GAMMA_MIN (VLV_DISPLAY_BASE + 0x67000)
+#define CGM_OFFSET 0x2000
+#define GAMMA_OFFSET 0x2000
+#define _PIPE_CGM_CONTROL(pipe) \
+ (PIPEA_CGM_CONTROL + (pipe * CGM_OFFSET))
+#define _PIPE_GAMMA_BASE(pipe) \
+ (PIPEA_CGM_GAMMA_MIN + (pipe * GAMMA_OFFSET))
We use the _PIPE() macro with tha pipe A and B registers for those ,
instead of having to defies the offsets.
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index d2674a6..21f0ac2 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -473,6 +473,12 @@ int intel_crtc_atomic_set_property(struct drm_crtc *crtc,
struct drm_property *property,
uint64_t val)
{
+ struct drm_device *dev = crtc->dev;
+ struct drm_mode_config *config = &dev->mode_config;
+
+ if (property == config->prop_palette_after_ctm)
+ return intel_color_manager_set_gamma(dev, &crtc->base, val);
+
DRM_DEBUG_KMS("Unknown crtc property '%s'\n", property->name);
return -EINVAL;
}
You are touching the hardware instead of staging the configuration?
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c
index 71b4c05..84cc3e47 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -27,6 +27,160 @@
#include "intel_color_manager.h"
+int chv_set_gamma(struct drm_device *dev, uint32_t blob_id,
+ struct drm_crtc *crtc)
+{
+ if (num_samples == 0) {
[...]
+ } else if (num_samples == CHV_8BIT_GAMMA_MAX_VALS) {
[...]
+ } else if (num_samples == CHV_10BIT_GAMMA_MAX_VALS) {
[...]
+ } else {
+ DRM_ERROR("Invalid number of samples for Gamma LUT\n");
+ return -EINVAL;
+ }
This means you're not accepting 256 values, something we do today with
the legacy ioctl() and something we probably want for generic userspace.
+ ret = drm_property_replace_global_blob(dev, &blob, length,
+ (void *) gamma_data, &crtc->base,
+ config->prop_palette_after_ctm);
+
+ if (ret) {
+ DRM_ERROR("Error updating Gamma blob\n");
+ return -EFAULT;
+ }
+
+ return ret;
+}
+
+int intel_color_manager_set_gamma(struct drm_device *dev,
+ struct drm_mode_object *obj, uint32_t blob_id)
+{
+ struct drm_crtc *crtc = obj_to_crtc(obj);
+
+ if (IS_CHERRYVIEW(dev))
+ return chv_set_gamma(dev, blob_id, crtc);
+
+ return -EINVAL;
+}
+
int get_chv_pipe_capabilities(struct drm_device *dev,
struct drm_color_caps *color_caps, struct drm_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h
index 32262ac..d83567a 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -31,6 +31,8 @@
#define CHV_PALETTE_STRUCT_VERSION 1
#define CHV_CTM_STRUCT_VERSION 1
#define CHV_PLATFORM_STRUCT_VERSION 1
+#define CHV_GAMMA_DATA_STRUCT_VERSION 1
+
#define CHV_MAX_PALETTE_CAPS_BEFORE_CTM 1
#define CHV_MAX_PALETTE_CAPS_AFTER_CTM 2
#define CHV_DEGAMMA_PRECISION 14
@@ -43,6 +45,16 @@
#define CHV_10BIT_GAMMA_MAX_VALS 257
#define CHV_8BIT_GAMMA_PRECISION 8
#define CHV_8BIT_GAMMA_MAX_VALS 256
+#define CHV_8BIT_GAMMA_MSB_SHIFT 8
+#define CHV_8BIT_GAMMA_SHIFT_RED_REG 16
+#define CHV_8BIT_GAMMA_SHIFT_GREEN_REG 8
+#define CHV_10BIT_GAMMA_MSB_SHIFT 6
+#define CHV_GAMMA_SHIFT_GREEN 16
+
#define CHV_CSC_COEFF_MAX_PRECISION 12
#define CHV_CSC_COEFF_MAX_INT 7
#define CHV_CSC_COEFF_MIN_INT -7
+
+/* CHV CGM Block */
+/* Bit 2 to be enabled in CGM block for CHV */
+#define CGM_GAMMA_EN 4
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 053ceb0..a7aaadf 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1453,5 +1453,7 @@ extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
/* intel_color_manager.c */
void intel_color_manager_attach(struct drm_device *dev,
struct drm_mode_object *mode_obj);
+int intel_color_manager_set_gamma(struct drm_device *dev,
+ struct drm_mode_object *obj, uint32_t blob_id);
#endif /* __INTEL_DRV_H__ */
--
2.4.5
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