Hi Gary,
On Mon, Jun 29, 2015 at 1:04 PM, Gary Bisson
<gary.bisson@xxxxxxxxxxxxxxxxxxx> wrote:
> Thank you for your e-mail and sorry for the delay in my response. I
> confirm this patch, ported over to my dtsi file, makes the HDMI and
> LVDS work together.
>
> I'll check with Eric but we will most likely use the same
> configuration for our platforms.
What do you mean by "use the same configuration for our platforms"?
I was planning to send the two attached patches.
Are you and Eric OK with them?
Regards,
Fabio Estevam
From 6a9a8e344eb672e7a847a4e81f0f289183ee0c39 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@xxxxxxxxxxxxx>
Date: Mon, 29 Jun 2015 11:07:07 -0300
Subject: [PATCH 1/3] ARM: dts: imx6qdl-sabrelite: Allow HDMI and LVDS to work simultaneously
Currently it is not possible to have HDMI and LVDS working simultaneously,
because both ports try to use PLL5.
Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
driven from independent sources.
With this change the LDB pixel clock goes to 68.57 MHz, which is still
within the valid range for the HSD100PXN1 LVDS panel.
Signed-off-by: Fabio Estevam <fabio.estevam@xxxxxxxxxxxxx>
---
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index e00c44f..d87e71c 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -148,6 +148,13 @@
status = "okay";
};
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
--
1.9.1
From 40ef0598f717d542d7c5ff2cd7e71d3df0693e1a Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@xxxxxxxxxxxxx>
Date: Mon, 29 Jun 2015 11:07:59 -0300
Subject: [PATCH 2/3] ARM: dts: imx6qdl-nitrogen6x: Allow HDMI and LVDS to work simultaneously
Currently it is not possible to have HDMI and LVDS working simultaneously,
because both ports try to use PLL5.
Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
driven from independent sources.
With this change the LDB pixel clock goes to 68.57 MHz, which is still
within the valid range for the HSD100PXN1 LVDS panel.
Signed-off-by: Fabio Estevam <fabio.estevam@xxxxxxxxxxxxx>
---
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 3af16df..1cba390 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -149,6 +149,13 @@
status = "okay";
};
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
--
1.9.1
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