Hi Philipp,
On 05/28/2015 03:58 AM, Philipp Zabel wrote:
> Hi Gary,
>
> Am Mittwoch, den 27.05.2015, 15:31 +0200 schrieb Gary Bisson:
>>> According to the kerneldoc comment for drm_fb_helper_initial_config
>>> (which is used by imx-drm via drm_fbdev_cma_init), it should set up a
>>> single /dev/fb cloned over all connectors. This works here with LVDS and
>>> HDMI.
>>
>> Does it require the two displays to have the exact same resolution?
>> I'm wondering what is wrong with my setup but with a 1024x768 LVDS and
>> a 1920x1080 HDMI display no image is shown on the HDMI (no signal).
>> The CRTC settings show that both have the same origin (0,0) so I
>> expected the LVDS to display a part of what the HDMI *should* display.
>
> No, but it does require the HDMI and LVDS display to use different clock
> sources (unless LVDS serializer clock happens to be the same as the HDMI
> pixel clock).
>
> I wonder what we should do about this for devices that have both LVDS
> and HDMI output and can only use PLL5 for both. Register a clock
> notifier that vetoes changes?
>
The LDB can be clocked from PLL2.
Here's a snippet of the clock tree from our 3.10.53 (Android) kernel
running both HDMI at 720P and the Hannstar hsd070pww1 panel:
pll2_pfd0_352m 1 1 500210526
ldb_di1_div_7 0 0 71458646
ldb_di1_div_sel 0 0 71458646
ldb_di1 0 0 71458646
ldb_di1_div_3_5 0 0 142917293
ldb_di0_div_7 1 1 71458646
ldb_di0_div_sel 1 1 71458646
ldb_di0 1 1 71458646
ipu1_di1_sel 1 1 71458646
ipu1_di1 1 1 71458646
ipu1_pclk1_sel 1 1 71458646
ipu1_pclk1_div 1 1
71458646
ipu1_pclk_1 1 1
71458646
I believe that the Freescale kernels always clock the LVDS display
bridge from PLL2 but perhaps not.
I'll test a dual-channel (1080P) display and trace the code
in this branch of our kernel tree:
https://github.com/boundarydevices/linux-imx6/tree/boundary-imx-kk4.4.3_2.0.0-ga/
> [...]
>>> For parallel and LVDS we'd either need to force the parallel panel to be
>>> clocked by the IPU internal clock, or move one or the other external
>>> clock source off of pll5_video.
>>
>> Do you have a preference for one solution over the other?
>
> That depends on the board. Is there an LVDS display that can be driven
> by a PLL other than PLL5? Since there is no sane way to change the
> LDB_DI parent in a running system, that should be configured in the
> device tree.
>
That would certainly be best (to allow the use of the more accurate
PLL5 in the normal case), but the PLL2 clock parent works well in
the most common cases.
Regards,
Eric
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