From: Stephane Viau <sviau@xxxxxxxxxxxxxx> Each interface (DSI/eDP/HDMI) has to control its own PLL. This change only add the register description for each one of them. Let's not make the register description common as some registers may not be implemented the same way for each interface PHY. v2: - Add description for more bit fields - Rebase on change "rnndb: dsi: Add DSI_LANE_CTRL info" Signed-off-by: Stephane Viau <sviau@xxxxxxxxxxxxxx> Signed-off-by: Hai Li <hali@xxxxxxxxxxxxxx> --- rnndb/dsi/dsi.xml | 80 +++++++++++++++++++++++++++++++++++++++++++++++++++++ rnndb/edp/edp.xml | 51 ++++++++++++++++++++++++++++++++++ rnndb/hdmi/hdmi.xml | 51 ++++++++++++++++++++++++++++++++++ 3 files changed, 182 insertions(+) diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi/dsi.xml index e645c45..d19bea9 100644 --- a/rnndb/dsi/dsi.xml +++ b/rnndb/dsi/dsi.xml @@ -445,4 +445,84 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x00018" name="CAL_PWR_CFG"/> </domain> +<domain name="DSI_28nm_PHY_PLL" width="32"> + <reg32 offset="0x00000" name="REFCLK_CFG"> + <bitfield name="DBLR" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x00004" name="POSTDIV1_CFG"/> + <reg32 offset="0x00008" name="CHGPUMP_CFG"/> + <reg32 offset="0x0000C" name="VCOLPF_CFG"/> + <reg32 offset="0x00010" name="VREG_CFG"> + <bitfield name="POSTDIV1_BYPASS_B" pos="1" type="boolean"/> + </reg32> + <reg32 offset="0x00014" name="PWRGEN_CFG"/> + <reg32 offset="0x00018" name="DMUX_CFG"/> + <reg32 offset="0x0001C" name="AMUX_CFG"/> + <reg32 offset="0x00020" name="GLB_CFG"> + <bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/> + <bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/> + <bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/> + <bitfield name="PLL_ENABLE" pos="3" type="boolean"/> + </reg32> + <reg32 offset="0x00024" name="POSTDIV2_CFG"/> + <reg32 offset="0x00028" name="POSTDIV3_CFG"/> + <reg32 offset="0x0002C" name="LPFR_CFG"/> + <reg32 offset="0x00030" name="LPFC1_CFG"/> + <reg32 offset="0x00034" name="LPFC2_CFG"/> + <reg32 offset="0x00038" name="SDM_CFG0"> + <bitfield name="BYP_DIV" low="0" high="5" type="uint"/> + <bitfield name="BYP" pos="6" type="boolean"/> + </reg32> + <reg32 offset="0x0003C" name="SDM_CFG1"> + <bitfield name="DC_OFFSET" low="0" high="5" type="uint"/> + <bitfield name="DITHER_EN" pos="6" type="uint"/> + </reg32> + <reg32 offset="0x00040" name="SDM_CFG2"> + <bitfield name="FREQ_SEED_7_0" low="0" high="7" type="uint"/> + </reg32> + <reg32 offset="0x00044" name="SDM_CFG3"> + <bitfield name="FREQ_SEED_15_8" low="0" high="7" type="uint"/> + </reg32> + <reg32 offset="0x00048" name="SDM_CFG4"/> + <reg32 offset="0x0004C" name="SSC_CFG0"/> + <reg32 offset="0x00050" name="SSC_CFG1"/> + <reg32 offset="0x00054" name="SSC_CFG2"/> + <reg32 offset="0x00058" name="SSC_CFG3"/> + <reg32 offset="0x0005C" name="LKDET_CFG0"/> + <reg32 offset="0x00060" name="LKDET_CFG1"/> + <reg32 offset="0x00064" name="LKDET_CFG2"/> + <reg32 offset="0x00068" name="TEST_CFG"> + <bitfield name="PLL_SW_RESET" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x0006C" name="CAL_CFG0"/> + <reg32 offset="0x00070" name="CAL_CFG1"/> + <reg32 offset="0x00074" name="CAL_CFG2"/> + <reg32 offset="0x00078" name="CAL_CFG3"/> + <reg32 offset="0x0007C" name="CAL_CFG4"/> + <reg32 offset="0x00080" name="CAL_CFG5"/> + <reg32 offset="0x00084" name="CAL_CFG6"/> + <reg32 offset="0x00088" name="CAL_CFG7"/> + <reg32 offset="0x0008C" name="CAL_CFG8"/> + <reg32 offset="0x00090" name="CAL_CFG9"/> + <reg32 offset="0x00094" name="CAL_CFG10"/> + <reg32 offset="0x00098" name="CAL_CFG11"/> + <reg32 offset="0x0009C" name="EFUSE_CFG"/> + <reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/> + <reg32 offset="0x000A4" name="CTRL_42"/> + <reg32 offset="0x000A8" name="CTRL_43"/> + <reg32 offset="0x000AC" name="CTRL_44"/> + <reg32 offset="0x000B0" name="CTRL_45"/> + <reg32 offset="0x000B4" name="CTRL_46"/> + <reg32 offset="0x000B8" name="CTRL_47"/> + <reg32 offset="0x000BC" name="CTRL_48"/> + <reg32 offset="0x000C0" name="STATUS"> + <bitfield name="PLL_RDY" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x000C4" name="DEBUG_BUS0"/> + <reg32 offset="0x000C8" name="DEBUG_BUS1"/> + <reg32 offset="0x000CC" name="DEBUG_BUS2"/> + <reg32 offset="0x000D0" name="DEBUG_BUS3"/> + <reg32 offset="0x000D4" name="CTRL_54"/> +</domain> + </database> diff --git a/rnndb/edp/edp.xml b/rnndb/edp/edp.xml index ea2a74b..00fc611 100644 --- a/rnndb/edp/edp.xml +++ b/rnndb/edp/edp.xml @@ -185,4 +185,55 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x0598" name="GLB_PHY_STATUS"/> </domain> +<domain name="EDP_28nm_PHY_PLL" width="32"> + <reg32 offset="0x00000" name="REFCLK_CFG"/> + <reg32 offset="0x00004" name="POSTDIV1_CFG"/> + <reg32 offset="0x00008" name="CHGPUMP_CFG"/> + <reg32 offset="0x0000C" name="VCOLPF_CFG"/> + <reg32 offset="0x00010" name="VREG_CFG"/> + <reg32 offset="0x00014" name="PWRGEN_CFG"/> + <reg32 offset="0x00018" name="DMUX_CFG"/> + <reg32 offset="0x0001C" name="AMUX_CFG"/> + <reg32 offset="0x00020" name="GLB_CFG"> + <bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/> + <bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/> + <bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/> + <bitfield name="PLL_ENABLE" pos="3" type="boolean"/> + </reg32> + <reg32 offset="0x00024" name="POSTDIV2_CFG"/> + <reg32 offset="0x00028" name="POSTDIV3_CFG"/> + <reg32 offset="0x0002C" name="LPFR_CFG"/> + <reg32 offset="0x00030" name="LPFC1_CFG"/> + <reg32 offset="0x00034" name="LPFC2_CFG"/> + <reg32 offset="0x00038" name="SDM_CFG0"/> + <reg32 offset="0x0003C" name="SDM_CFG1"/> + <reg32 offset="0x00040" name="SDM_CFG2"/> + <reg32 offset="0x00044" name="SDM_CFG3"/> + <reg32 offset="0x00048" name="SDM_CFG4"/> + <reg32 offset="0x0004C" name="SSC_CFG0"/> + <reg32 offset="0x00050" name="SSC_CFG1"/> + <reg32 offset="0x00054" name="SSC_CFG2"/> + <reg32 offset="0x00058" name="SSC_CFG3"/> + <reg32 offset="0x0005C" name="LKDET_CFG0"/> + <reg32 offset="0x00060" name="LKDET_CFG1"/> + <reg32 offset="0x00064" name="LKDET_CFG2"/> + <reg32 offset="0x00068" name="TEST_CFG"> + <bitfield name="PLL_SW_RESET" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x0006C" name="CAL_CFG0"/> + <reg32 offset="0x00070" name="CAL_CFG1"/> + <reg32 offset="0x00074" name="CAL_CFG2"/> + <reg32 offset="0x00078" name="CAL_CFG3"/> + <reg32 offset="0x0007C" name="CAL_CFG4"/> + <reg32 offset="0x00080" name="CAL_CFG5"/> + <reg32 offset="0x00084" name="CAL_CFG6"/> + <reg32 offset="0x00088" name="CAL_CFG7"/> + <reg32 offset="0x0008C" name="CAL_CFG8"/> + <reg32 offset="0x00090" name="CAL_CFG9"/> + <reg32 offset="0x00094" name="CAL_CFG10"/> + <reg32 offset="0x00098" name="CAL_CFG11"/> + <reg32 offset="0x0009C" name="EFUSE_CFG"/> + <reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/> +</domain> + </database> diff --git a/rnndb/hdmi/hdmi.xml b/rnndb/hdmi/hdmi.xml index 64393b4..ddab016 100644 --- a/rnndb/hdmi/hdmi.xml +++ b/rnndb/hdmi/hdmi.xml @@ -569,4 +569,55 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x00048" name="BIST_PATN3"/> </domain> +<domain name="HDMI_28nm_PHY_PLL" width="32"> + <reg32 offset="0x00000" name="REFCLK_CFG"/> + <reg32 offset="0x00004" name="POSTDIV1_CFG"/> + <reg32 offset="0x00008" name="CHGPUMP_CFG"/> + <reg32 offset="0x0000C" name="VCOLPF_CFG"/> + <reg32 offset="0x00010" name="VREG_CFG"/> + <reg32 offset="0x00014" name="PWRGEN_CFG"/> + <reg32 offset="0x00018" name="DMUX_CFG"/> + <reg32 offset="0x0001C" name="AMUX_CFG"/> + <reg32 offset="0x00020" name="GLB_CFG"> + <bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/> + <bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/> + <bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/> + <bitfield name="PLL_ENABLE" pos="3" type="boolean"/> + </reg32> + <reg32 offset="0x00024" name="POSTDIV2_CFG"/> + <reg32 offset="0x00028" name="POSTDIV3_CFG"/> + <reg32 offset="0x0002C" name="LPFR_CFG"/> + <reg32 offset="0x00030" name="LPFC1_CFG"/> + <reg32 offset="0x00034" name="LPFC2_CFG"/> + <reg32 offset="0x00038" name="SDM_CFG0"/> + <reg32 offset="0x0003C" name="SDM_CFG1"/> + <reg32 offset="0x00040" name="SDM_CFG2"/> + <reg32 offset="0x00044" name="SDM_CFG3"/> + <reg32 offset="0x00048" name="SDM_CFG4"/> + <reg32 offset="0x0004C" name="SSC_CFG0"/> + <reg32 offset="0x00050" name="SSC_CFG1"/> + <reg32 offset="0x00054" name="SSC_CFG2"/> + <reg32 offset="0x00058" name="SSC_CFG3"/> + <reg32 offset="0x0005C" name="LKDET_CFG0"/> + <reg32 offset="0x00060" name="LKDET_CFG1"/> + <reg32 offset="0x00064" name="LKDET_CFG2"/> + <reg32 offset="0x00068" name="TEST_CFG"> + <bitfield name="PLL_SW_RESET" pos="0" type="boolean"/> + </reg32> + <reg32 offset="0x0006C" name="CAL_CFG0"/> + <reg32 offset="0x00070" name="CAL_CFG1"/> + <reg32 offset="0x00074" name="CAL_CFG2"/> + <reg32 offset="0x00078" name="CAL_CFG3"/> + <reg32 offset="0x0007C" name="CAL_CFG4"/> + <reg32 offset="0x00080" name="CAL_CFG5"/> + <reg32 offset="0x00084" name="CAL_CFG6"/> + <reg32 offset="0x00088" name="CAL_CFG7"/> + <reg32 offset="0x0008C" name="CAL_CFG8"/> + <reg32 offset="0x00090" name="CAL_CFG9"/> + <reg32 offset="0x00094" name="CAL_CFG10"/> + <reg32 offset="0x00098" name="CAL_CFG11"/> + <reg32 offset="0x0009C" name="EFUSE_CFG"/> + <reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/> +</domain> + </database> -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
