Am Montag, den 02.03.2015, 16:40 +0100 schrieb Lucas Stach: > Am Montag, den 02.03.2015, 16:24 +0100 schrieb Philipp Zabel: > > This patch allows the IPU to divide the 27 MHz input clock from > > the TVE by two to obtain the 13.5 MHz pixel clock needed for > > NTSC/PAL SD modes. > > > > Signed-off-by: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx> > > --- > > drivers/gpu/drm/imx/ipuv3-crtc.c | 7 +++++-- > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c > > index 35a3375..11a8d868 100644 > > --- a/drivers/gpu/drm/imx/ipuv3-crtc.c > > +++ b/drivers/gpu/drm/imx/ipuv3-crtc.c > > @@ -161,13 +161,16 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, > > __func__, encoder_types); > > > > /* > > - * If we have DAC, TVDAC or LDB, then we need the IPU DI clock > > - * to be the same as the LDB DI clock. > > + * If we have DAC or LDB, then we need the IPU DI clock to be > > + * the same as the LDB DI clock. For TVDAC, derive the IPU DI > > + * clock from 27 MHz TVE_DI clock, but allow to divide it. > > */ > > if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) | > > BIT(DRM_MODE_ENCODER_TVDAC) | > > I suppose the above line has to be removed for this to work properly. You are right. I'll fix that. > > BIT(DRM_MODE_ENCODER_LVDS))) > > sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT; > > + else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC)) > > + sig_cfg.clkflags = IPU_DI_CLKMODE_EXT; > > else > > sig_cfg.clkflags = 0; > > thanks Philipp _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
