Hello radeon devs, I have been trying to find out more about VM implementation on SI+ hw, but unfortunately I could not find much in the public documents[0]. SI ISA manual suggests that there is a limited form of privileged mode on these chips, so I wondered if it could be used for VM management too (the docs only deal with numerical exceptions). Or does it always have to be handled by host (driver)? One of the older patches [1] mentions different page sizes, is there any public documentation on things like page table format, and GPU MMU hierarchy? I could only get limited picture going through the code and comments. thank you, Jan [0]http://developer.amd.com/resources/documentation-articles/developer-guides-manuals/ [1]http://lists.freedesktop.org/archives/dri-devel/2014-May/058858.html -- Jan Vesely <jan.vesely@xxxxxxxxxxx>
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