On Thu, Feb 12, 2015 at 02:01:24PM +0800, Liu Ying wrote:
> If no best divider is normally found, we will try to use the maximum divider.
> We should not set the parent clock rate to be 1Hz by force for being rounded.
> Instead, we should take the maximum divider as a base and calculate a correct
> parent clock rate for being rounded.
Please add an explanation why you think the current code is wrong and
what this actually fixes, maybe an example?
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index c0a842b..f641d4b 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -311,7 +311,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
>
> if (!bestdiv) {
> bestdiv = _get_maxdiv(divider);
> - *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
> + *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
> + MULT_ROUND_UP(rate, bestdiv));
When getting into the if(!bestdiv) it means that the lowest possible
rate we can archieve is still higher than the target rate, so setting
the parent rate as low as possible seems sane to me. Why do you think
this is wrong? In which case this even makes a difference?
Sascha
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