RK3288 hdmi eye-diagram test would fail when pixel clock is 148.5MHz, and single-ended test would failed when display mode is 74.25MHz. - Fix some code style, leave space for next patches. - For hdmi eye-diagram test, we turn on the Transmitter Trailer-B and improve slopeboost to 25%-30% decrease. - For hdmi single-ended test, we set CKLVL & TXLVL to 17 when pixel clock is 74.25MHz, keep CKLVL & TXLVL to 13 when pixel clock is 148.5MHz. Yakir Yang (1): drm: bridge/dw_hdmi: fixed codec style drivers/gpu/drm/bridge/dw_hdmi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
