Comment # 21
on bug 73378
from Chernovsky Oleg
(In reply to Christian König from comment #20) > (In reply to Chernovsky Oleg from comment #15) > > I can help with code here. > > > > What should be implemented, roughly? > > Sounds good. I assume you got a card with that problem. > > First of all try if UVD works otherwise. E.g. we raise the clocks for the > boot up test (and lower them again after that), but that's actually not > necessary most of the time. > > So get into radeon_uvd_send_upll_ctlreq, just comment out the error return > value and pretend everything worked fine. > > Then check if the following IB test works or not. > > If that doesn't work the input clocks to the PLL doesn't seem to work and we > have a clock routing problem or something like that. If that works the PLL > just doesn't likes our parameters and we need to figure out why. > > Feel free to contact me by mail if you have more questions. > > Thanks, > Christian. Yes, I have a card with that problem Ok Christian, I'll be doing tests on this weekend and report here. If this won't work out, I'll look through the code Alex mentioned. Thanks for clarifications!
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