This allows for proper PPS during enable/disable of BYT-T platforms
where these signals are routed through PMIC. Needs DRM_PANEL to be
selected by default as well
v2: Adapt to panel find function name change in drm_panel
Signed-off-by: Shobhit Kumar <shobhit.kumar@xxxxxxxxx>
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/intel-panel-crystalcove.c | 1 +
drivers/gpu/drm/i915/intel_dsi.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/intel_dsi.h | 6 ++++++
4 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 0510ef0..bacbc06 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -18,6 +18,7 @@ config DRM_I915
select INPUT if ACPI
select ACPI_VIDEO if ACPI
select ACPI_BUTTON if ACPI
+ select DRM_PANEL
help
Choose this option if you have a system that has "Intel Graphics
Media Accelerator" or "HD Graphics" integrated graphics,
diff --git a/drivers/gpu/drm/i915/intel-panel-crystalcove.c b/drivers/gpu/drm/i915/intel-panel-crystalcove.c
index a6aefa3..0f129b2 100644
--- a/drivers/gpu/drm/i915/intel-panel-crystalcove.c
+++ b/drivers/gpu/drm/i915/intel-panel-crystalcove.c
@@ -154,6 +154,7 @@ static struct platform_driver crystalcove_panel_driver = {
module_platform_driver(crystalcove_panel_driver);
+MODULE_ALIAS();
MODULE_AUTHOR("Shobhit Kumar <shobhit.kumar@xxxxxxxxxxxxxxx");
MODULE_DESCRIPTION("Intel Crystal Cove Panel Driver");
MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 42b6d6f..6857d19 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -26,6 +26,7 @@
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
+#include <drm/drm_panel.h>
#include <drm/i915_drm.h>
#include <linux/slab.h>
#include "i915_drv.h"
@@ -230,6 +231,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
+ drm_panel_enable(intel_dsi->panel);
+
/* Disable DPOunit clock gating, can stall pipe
* and we need DPLL REFA always enabled */
tmp = I915_READ(DPLL(pipe));
@@ -392,6 +395,8 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
msleep(intel_dsi->panel_off_delay);
msleep(intel_dsi->panel_pwr_cycle_delay);
+
+ drm_panel_disable(intel_dsi->panel);
}
static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
@@ -896,6 +901,17 @@ void intel_dsi_init(struct drm_device *dev)
fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
+ /* Initialize the PMIC based drm_panel if available on the platform */
+ if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
+ intel_dsi->panel = drm_find_panel_by_name("crystal_cove_panel");
+ if (!intel_dsi->panel) {
+ DRM_ERROR("PMIC Panel control will not work !!\n");
+ return;
+ }
+
+ drm_panel_attach(intel_dsi->panel, connector);
+ }
+
return;
err:
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 8fe2064..4a9242d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -33,6 +33,9 @@
#define DSI_DUAL_LINK_FRONT_BACK 1
#define DSI_DUAL_LINK_PIXEL_ALT 2
+#define PPS_BLC_PMIC 0
+#define PPS_BLC_SOC 1
+
struct intel_dsi_device {
unsigned int panel_id;
const char *name;
@@ -83,6 +86,8 @@ struct intel_dsi {
struct intel_connector *attached_connector;
+ struct drm_panel *panel;
+
/* bit mask of ports being driven */
u16 ports;
@@ -116,6 +121,7 @@ struct intel_dsi {
u32 dphy_reg;
u32 video_frmt_cfg_bits;
u16 lp_byte_clk;
+ u8 pps_blc;
/* timeouts in byte clocks */
u16 lp_rx_timeout;
--
1.9.1
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