On Mon, Dec 15, 2014 at 12:26:46PM -0800, Ben Widawsky wrote:
> From: Ben Widawsky <ben@xxxxxxxxxxxx>
>
> When the original drm code was written there were no centralized functions for
> doing a coordinated wbinvd across all CPUs. Now (since 2010) there are, so use
> them instead of rolling a new one.
>
> v2: On x86 UP systems the wbinvd_on_all_cpus() is defined as a static inline in
> smp.h. We must therefore include this file so we don't get compiler errors.
> This error was found by 0-DAY kernel test infrastructure. We only need this for
> x86.
Oh dear UP ;-) Thanks for the quick updated, new patch merged to dinq.
-Daniel
>
> Cc: Intel GFX <intel-gfx@xxxxxxxxxxxxxxxxxxxxx>
> Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx>
> Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> (v1)
> ---
> drivers/gpu/drm/drm_cache.c | 13 ++++---------
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index a6b6906..9a62d7a 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -32,6 +32,7 @@
> #include <drm/drmP.h>
>
> #if defined(CONFIG_X86)
> +#include <asm/smp.h>
>
> /*
> * clflushopt is an unordered instruction which needs fencing with mfence or
> @@ -64,12 +65,6 @@ static void drm_cache_flush_clflush(struct page *pages[],
> drm_clflush_page(*pages++);
> mb();
> }
> -
> -static void
> -drm_clflush_ipi_handler(void *null)
> -{
> - wbinvd();
> -}
> #endif
>
> void
> @@ -82,7 +77,7 @@ drm_clflush_pages(struct page *pages[], unsigned long num_pages)
> return;
> }
>
> - if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0)
> + if (wbinvd_on_all_cpus())
> printk(KERN_ERR "Timed out waiting for cache flush.\n");
>
> #elif defined(__powerpc__)
> @@ -121,7 +116,7 @@ drm_clflush_sg(struct sg_table *st)
> return;
> }
>
> - if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0)
> + if (wbinvd_on_all_cpus())
> printk(KERN_ERR "Timed out waiting for cache flush.\n");
> #else
> printk(KERN_ERR "Architecture has no drm_cache.c support\n");
> @@ -144,7 +139,7 @@ drm_clflush_virt_range(void *addr, unsigned long length)
> return;
> }
>
> - if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0)
> + if (wbinvd_on_all_cpus())
> printk(KERN_ERR "Timed out waiting for cache flush.\n");
> #else
> printk(KERN_ERR "Architecture has no drm_cache.c support\n");
> --
> 2.1.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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