Comment # 51
on bug 82201
from Sebastian Parborg
Hmm, seems like it detects the correct max clock...
switching from power state:
ui class: performance
internal class: none
caps:
uvd vclk: 0 dclk: 0
power level 0 sclk: 30000 mclk: 15000 pcie gen: 2 pcie lanes: 16
power level 1 sclk: 105000 mclk: 135000 pcie gen: 2 pcie lanes: 16
status: c r
switching to power state:
ui class: performance
internal class: none
caps:
uvd vclk: 0 dclk: 0
power level 0 sclk: 30000 mclk: 15000 pcie gen: 2 pcie lanes: 16
power level 1 sclk: 105000 mclk: 135000 pcie gen: 2 pcie lanes: 16
status: c r
So it seems like the reclocking itself is failing somehow.
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