The HDMI path introduce a delay of 6 pixels. This delay should be take into account while programming VTG for the HDMI. Without this delay, the HDMI active window area is shift of 6 pixel on the right. Set also timing for DVO output. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@xxxxxxxxxx> --- drivers/gpu/drm/sti/sti_vtg.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/sti/sti_vtg.c b/drivers/gpu/drm/sti/sti_vtg.c index 740d6e3..ce7c0c9 100644 --- a/drivers/gpu/drm/sti/sti_vtg.c +++ b/drivers/gpu/drm/sti/sti_vtg.c @@ -55,6 +55,9 @@ #define VTG_IRQ_TOP BIT(1) #define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM) +/* Delay introduced by the HDMI in nb of pixel */ +#define HDMI_DELAY (6) + /* delay introduced by the Arbitrary Waveform Generator in nb of pixels */ #define AWG_DELAY_HD (-9) #define AWG_DELAY_ED (-8) @@ -133,10 +136,10 @@ static void vtg_set_mode(struct sti_vtg *vtg, writel(tmp, vtg->regs + VTG_VID_TFS); writel(tmp, vtg->regs + VTG_VID_BFS); - /* prepare VTG set 1 and 2 for HDMI and VTG set 3 for HD DAC */ - tmp = (mode->hsync_end - mode->hsync_start) << 16; + /* prepare VTG set 1 for HDMI */ + tmp = (mode->hsync_end - mode->hsync_start + HDMI_DELAY) << 16; + tmp |= HDMI_DELAY; writel(tmp, vtg->regs + VTG_H_HD_1); - writel(tmp, vtg->regs + VTG_H_HD_2); tmp = (mode->vsync_end - mode->vsync_start + 1) << 16; tmp |= 1; @@ -146,6 +149,11 @@ static void vtg_set_mode(struct sti_vtg *vtg, writel(0, vtg->regs + VTG_BOT_V_HD_1); /* prepare VTG set 2 for for HD DCS */ + tmp = (mode->hsync_end - mode->hsync_start) << 16; + writel(tmp, vtg->regs + VTG_H_HD_2); + + tmp = (mode->vsync_end - mode->vsync_start + 1) << 16; + tmp |= 1; writel(tmp, vtg->regs + VTG_TOP_V_VD_2); writel(tmp, vtg->regs + VTG_BOT_V_VD_2); writel(0, vtg->regs + VTG_TOP_V_HD_2); @@ -166,6 +174,17 @@ static void vtg_set_mode(struct sti_vtg *vtg, writel(tmp, vtg->regs + VTG_TOP_V_HD_3); writel(tmp, vtg->regs + VTG_BOT_V_HD_3); + /* Prepare VTG set 4 for DVO */ + tmp = (mode->hsync_end - mode->hsync_start) << 16; + writel(tmp, vtg->regs + VTG_H_HD_4); + + tmp = (mode->vsync_end - mode->vsync_start + 1) << 16; + tmp |= 1; + writel(tmp, vtg->regs + VTG_TOP_V_VD_4); + writel(tmp, vtg->regs + VTG_BOT_V_VD_4); + writel(0, vtg->regs + VTG_TOP_V_HD_4); + writel(0, vtg->regs + VTG_BOT_V_HD_4); + /* mode */ writel(type, vtg->regs + VTG_MODE); } -- 1.9.1 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
