Re: [PATCH 01/11] drm/radeon: rework vm_flush parameters

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Am 19.11.2014 um 19:28 schrieb Alex Deucher:

On Wed, Nov 19, 2014 at 8:01 AM, Christian König
<deathsimple@xxxxxxxxxxx> wrote:

From: Christian König <christian.koenig@xxxxxxx>

Use ring structure instead of index and provide vm_id and pd_addr separately.

Signed-off-by: Christian König <christian.koenig@xxxxxxx>

Pushed to my 3.19-wip tree.  I'll send out a new radeon drm-next pull
request later today or tomorrow.
Please note that I had to fix another bug in the last patch pointed out by Kai Wasserbäch. 

The updated patch should already be in your inbox.

Christian.



Alex


---
  drivers/gpu/drm/radeon/cik.c         | 23 ++++++++++-------------
  drivers/gpu/drm/radeon/cik_sdma.c    | 22 +++++++++-------------
  drivers/gpu/drm/radeon/ni.c          | 14 +++++---------
  drivers/gpu/drm/radeon/ni_dma.c      | 14 +++++---------
  drivers/gpu/drm/radeon/radeon.h      |  5 +++--
  drivers/gpu/drm/radeon/radeon_asic.h | 18 ++++++++++++------
  drivers/gpu/drm/radeon/radeon_vm.c   |  3 ++-
  drivers/gpu/drm/radeon/si.c          | 18 +++++++-----------
  drivers/gpu/drm/radeon/si_dma.c      | 19 ++++++++-----------
  9 files changed, 61 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 57a359d..d52ead9 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -5967,26 +5967,23 @@ static void cik_vm_decode_fault(struct radeon_device *rdev,
   * Update the page table base and flush the VM TLB
   * using the CP (CIK).
   */
-void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
+void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
+                 unsigned vm_id, uint64_t pd_addr)
  {
-       struct radeon_ring *ring = &rdev->ring[ridx];
-       int usepfp = (ridx == RADEON_RING_TYPE_GFX_INDEX);
-
-       if (vm == NULL)
-               return;
+       int usepfp = (ring->idx == RADEON_RING_TYPE_GFX_INDEX);

         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
                                  WRITE_DATA_DST_SEL(0)));
-       if (vm->id < 8) {
+       if (vm_id < 8) {
                 radeon_ring_write(ring,
-                                 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
+                                 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
         } else {
                 radeon_ring_write(ring,
-                                 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
+                                 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
         }
         radeon_ring_write(ring, 0);
-       radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
+       radeon_ring_write(ring, pd_addr >> 12);

         /* update SH_MEM_* regs */
         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
@@ -5994,7 +5991,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
                                  WRITE_DATA_DST_SEL(0)));
         radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
         radeon_ring_write(ring, 0);
-       radeon_ring_write(ring, VMID(vm->id));
+       radeon_ring_write(ring, VMID(vm_id));

         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
@@ -6015,7 +6012,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
         radeon_ring_write(ring, VMID(0));

         /* HDP flush */
-       cik_hdp_flush_cp_ring_emit(rdev, ridx);
+       cik_hdp_flush_cp_ring_emit(rdev, ring->idx);

         /* bits 0-15 are the VM contexts0-15 */
         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
@@ -6023,7 +6020,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
                                  WRITE_DATA_DST_SEL(0)));
         radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
         radeon_ring_write(ring, 0);
-       radeon_ring_write(ring, 1 << vm->id);
+       radeon_ring_write(ring, 1 << vm_id);

         /* compute doesn't have PFP */
         if (usepfp) {
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 4e8432d..7470a2e 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -901,25 +901,21 @@ void cik_sdma_vm_pad_ib(struct radeon_ib *ib)
   * Update the page table base and flush the VM TLB
   * using sDMA (CIK).
   */
-void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
+void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
+                     unsigned vm_id, uint64_t pd_addr)
  {
-       struct radeon_ring *ring = &rdev->ring[ridx];
-
-       if (vm == NULL)
-               return;
-
         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-       if (vm->id < 8) {
-               radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
+       if (vm_id < 8) {
+               radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
         } else {
-               radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
+               radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
         }
-       radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
+       radeon_ring_write(ring, pd_addr >> 12);

         /* update SH_MEM_* regs */
         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
         radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
-       radeon_ring_write(ring, VMID(vm->id));
+       radeon_ring_write(ring, VMID(vm_id));

         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
         radeon_ring_write(ring, SH_MEM_BASES >> 2);
@@ -942,11 +938,11 @@ void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm
         radeon_ring_write(ring, VMID(0));

         /* flush HDP */
-       cik_sdma_hdp_flush_ring_emit(rdev, ridx);
+       cik_sdma_hdp_flush_ring_emit(rdev, ring->idx);

         /* flush TLB */
         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
         radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
-       radeon_ring_write(ring, 1 << vm->id);
+       radeon_ring_write(ring, 1 << vm_id);
  }

diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 3faee58..bee432d 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -2502,15 +2502,11 @@ void cayman_vm_decode_fault(struct radeon_device *rdev,
   * Update the page table base and flush the VM TLB
   * using the CP (cayman-si).
   */
-void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
+void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
+                    unsigned vm_id, uint64_t pd_addr)
  {
-       struct radeon_ring *ring = &rdev->ring[ridx];
-
-       if (vm == NULL)
-               return;
-
-       radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
-       radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
+       radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0));
+       radeon_ring_write(ring, pd_addr >> 12);

         /* flush hdp cache */
         radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
@@ -2518,7 +2514,7 @@ void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)

         /* bits 0-7 are the VM contexts0-7 */
         radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
-       radeon_ring_write(ring, 1 << vm->id);
+       radeon_ring_write(ring, 1 << vm_id);

         /* sync PFP to ME, otherwise we might get invalid PFP reads */
         radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
diff --git a/drivers/gpu/drm/radeon/ni_dma.c b/drivers/gpu/drm/radeon/ni_dma.c
index f26f0a9..5a72404 100644
--- a/drivers/gpu/drm/radeon/ni_dma.c
+++ b/drivers/gpu/drm/radeon/ni_dma.c
@@ -446,16 +446,12 @@ void cayman_dma_vm_pad_ib(struct radeon_ib *ib)
                 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
  }

-void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
+void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
+                        unsigned vm_id, uint64_t pd_addr)
  {
-       struct radeon_ring *ring = &rdev->ring[ridx];
-
-       if (vm == NULL)
-               return;
-
         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
-       radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
-       radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
+       radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2));
+       radeon_ring_write(ring, pd_addr >> 12);

         /* flush hdp cache */
         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
@@ -465,6 +461,6 @@ void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm
         /* bits 0-7 are the VM contexts0-7 */
         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
         radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
-       radeon_ring_write(ring, 1 << vm->id);
+       radeon_ring_write(ring, 1 << vm_id);
  }

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 908f349..5d913ef 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1790,7 +1790,8 @@ struct radeon_asic_ring {
         void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
         bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
                                struct radeon_semaphore *semaphore, bool emit_wait);
-       void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+       void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
+                        unsigned vm_id, uint64_t pd_addr);

         /* testing functions */
         int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
@@ -2836,7 +2837,7 @@ static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
  #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
  #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
  #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
-#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
+#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
  #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
  #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
  #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index d8ace5b..2a45d54 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -599,7 +599,8 @@ int cayman_asic_reset(struct radeon_device *rdev);
  void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  int cayman_vm_init(struct radeon_device *rdev);
  void cayman_vm_fini(struct radeon_device *rdev);
-void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
+                    unsigned vm_id, uint64_t pd_addr);
  uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
  int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
  int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
@@ -624,7 +625,8 @@ void cayman_dma_vm_set_pages(struct radeon_device *rdev,
                              uint32_t incr, uint32_t flags);
  void cayman_dma_vm_pad_ib(struct radeon_ib *ib);

-void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
+                        unsigned vm_id, uint64_t pd_addr);

  u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
                         struct radeon_ring *ring);
@@ -699,7 +701,8 @@ int si_irq_set(struct radeon_device *rdev);
  int si_irq_process(struct radeon_device *rdev);
  int si_vm_init(struct radeon_device *rdev);
  void si_vm_fini(struct radeon_device *rdev);
-void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
+                unsigned vm_id, uint64_t pd_addr);
  int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
  struct radeon_fence *si_copy_dma(struct radeon_device *rdev,
                                  uint64_t src_offset, uint64_t dst_offset,
@@ -721,7 +724,8 @@ void si_dma_vm_set_pages(struct radeon_device *rdev,
                          uint64_t addr, unsigned count,
                          uint32_t incr, uint32_t flags);

-void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
+                    unsigned vm_id, uint64_t pd_addr);
  u32 si_get_xclk(struct radeon_device *rdev);
  uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
  int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
@@ -793,7 +797,8 @@ int cik_irq_set(struct radeon_device *rdev);
  int cik_irq_process(struct radeon_device *rdev);
  int cik_vm_init(struct radeon_device *rdev);
  void cik_vm_fini(struct radeon_device *rdev);
-void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
+                 unsigned vm_id, uint64_t pd_addr);

  void cik_sdma_vm_copy_pages(struct radeon_device *rdev,
                             struct radeon_ib *ib,
@@ -811,7 +816,8 @@ void cik_sdma_vm_set_pages(struct radeon_device *rdev,
                            uint32_t incr, uint32_t flags);
  void cik_sdma_vm_pad_ib(struct radeon_ib *ib);

-void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
+                     unsigned vm_id, uint64_t pd_addr);
  int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
  u32 cik_gfx_get_rptr(struct radeon_device *rdev,
                      struct radeon_ring *ring);
diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c
index dfde266..9d0f87b 100644
--- a/drivers/gpu/drm/radeon/radeon_vm.c
+++ b/drivers/gpu/drm/radeon/radeon_vm.c
@@ -243,7 +243,8 @@ void radeon_vm_flush(struct radeon_device *rdev,
         if (!vm->last_flush || pd_addr != vm->pd_gpu_addr) {
                 trace_radeon_vm_flush(pd_addr, ring, vm->id);
                 vm->pd_gpu_addr = pd_addr;
-               radeon_ring_vm_flush(rdev, ring, vm);
+               radeon_ring_vm_flush(rdev, &rdev->ring[ring],
+                                    vm->id, vm->pd_gpu_addr);
         }
  }

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index eeea5b6..e91968b 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -5020,27 +5020,23 @@ static void si_vm_decode_fault(struct radeon_device *rdev,
                block, mc_id);
  }

-void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
+void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
+                unsigned vm_id, uint64_t pd_addr)
  {
-       struct radeon_ring *ring = &rdev->ring[ridx];
-
-       if (vm == NULL)
-               return;
-
         /* write new base address */
         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
                                  WRITE_DATA_DST_SEL(0)));

-       if (vm->id < 8) {
+       if (vm_id < 8) {
                 radeon_ring_write(ring,
-                                 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
+                                 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
         } else {
                 radeon_ring_write(ring,
-                                 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
+                                 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
         }
         radeon_ring_write(ring, 0);
-       radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
+       radeon_ring_write(ring, pd_addr >> 12);

         /* flush hdp cache */
         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
@@ -5056,7 +5052,7 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
                                  WRITE_DATA_DST_SEL(0)));
         radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
         radeon_ring_write(ring, 0);
-       radeon_ring_write(ring, 1 << vm->id);
+       radeon_ring_write(ring, 1 << vm_id);

         /* sync PFP to ME, otherwise we might get invalid PFP reads */
         radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
diff --git a/drivers/gpu/drm/radeon/si_dma.c b/drivers/gpu/drm/radeon/si_dma.c
index b58f12b..e8bc0a5 100644
--- a/drivers/gpu/drm/radeon/si_dma.c
+++ b/drivers/gpu/drm/radeon/si_dma.c
@@ -185,20 +185,17 @@ void si_dma_vm_set_pages(struct radeon_device *rdev,
         }
  }

-void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
-{
-       struct radeon_ring *ring = &rdev->ring[ridx];
-
-       if (vm == NULL)
-               return;
+void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
+                    unsigned vm_id, uint64_t pd_addr)

+{
         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
-       if (vm->id < 8) {
-               radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
+       if (vm_id < 8) {
+               radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2));
         } else {
-               radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2));
+               radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2));
         }
-       radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
+       radeon_ring_write(ring, pd_addr >> 12);

         /* flush hdp cache */
         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
@@ -208,7 +205,7 @@ void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
         /* bits 0-7 are the VM contexts0-7 */
         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
         radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
-       radeon_ring_write(ring, 1 << vm->id);
+       radeon_ring_write(ring, 1 << vm_id);
  }

  /**
--
1.9.1



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