Hi Dave,
drm-intel-next-2014-11-07:
- skl watermarks code (Damien, Vandana, Pradeep)
- reworked audio codec /eld handling code (Jani)
- rework the mmio_flip code to use the vblank evade logic and wait for rendering
using the standard wait_seqno interface (Ander)
- skl forcewake support (Zhe Wang)
- refactor the chv interrupt code to use functions shared with vlv (Ville)
- prep work for different global gtt views (Tvrtko Ursulin)
- precompute the display PLL config before touching hw state (Ander)
- completely reworked panel power sequencer code for chv/vlv (Ville)
- pre work to split the plane update code into a prepare and commit phase
(Gustavo Padovan)
- golden context for skl (Armin Reese)
- as usual tons of fixes and improvements all over
The pll rework from Ander resulted in a few black screens, so 2 fixup
patches on top. And a backmerge because I needed that for the next round
of patches.
And as discussed on irc because misaligned QA test cycle on our end there
will be one more pull request for 3.19 and that's it.
Cheers, Daniel
The following changes since commit cc7096fb6d1dfbdac5e7e2675c046fd40646cc66:
drm/mode: document path property and function to set it. (v1.1) (2014-11-10 10:21:14 +1000)
are available in the git repository at:
git://anongit.freedesktop.org/drm-intel tags/drm-intel-next-2014-11-07-fixups
for you to fetch changes up to e1f234bde6edb2bcdb763c90076b9484e4c71a33:
drm/i915: Use correct pipe config to update pll dividers. V2 (2014-11-14 10:28:52 +0100)
----------------------------------------------------------------
Ander Conselvan de Oliveira (15):
drm/i915: Make *_crtc_mode_set work on new_config
drm/i915: Convert shared dpll reference count to a crtc mask
drm/i915: Move dpll crtc_mask and hw_state fields into separate struct
drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs
drm/i915: Covert HSW+ to choose DPLLS before disabling CRTCs
drm/i915: Covert ILK-IVB to choose DPLLS before disabling CRTCs
drm/i915: Covert remaining platforms to choose DPLLS before disabling CRTCs
drm/i915: Remove crtc_mode_set() hook
drm/i915: Don't store current shared DPLL in the new pipe_config
drm/i915: Add kerneldoc for intel_pipe_update_{start, end}
drm/i915: Remove modeset lock check from intel_pipe_update_start()
drm/i915: Use vblank evade mechanism in mmio_flip
drm/i915: Make __wait_seqno non-static and rename to __i915_wait_seqno
drm/i915: Make mmio flip wait for seqno in the work function
drm/i915: Plug memory leak in intel_shared_dpll_start_config()
Armin Reese (2):
drm/i915 Update Gen8 golden context batch buffer
drm/i915 Add golden context support for Gen9
Bob Paauwe (1):
drm/i915: Use correct pipe config to update pll dividers. V2
Brad Volkin (1):
drm/i915: Abort command parsing for chained batches
Chris Wilson (3):
drm/i915: Only mark as map-and-fenceable when bound into the GGTT
drm/i915: Request PIN_GLOBAL when pinning a vma for GTT relocations
drm/i915: Report the actual swizzling back to userspace
Damien Lespiau (24):
drm/i915: Remove unnecessary test on the gen in intel_do_mmio_flip()
drm/i915: Make intel_pipe_has_type() take an output type enum
drm/i915: Remove unused WATCH_GTT define
drm/i915: Removed orphaned prototype intel_dp_handle_hpd_irq()
drm/i915: Remove orphaned prototype gen6_set_pm_mask()
drm/i915/skl: Add DDB allocation management structures
drm/i915/skl: Allocate DDB portions for display planes
drm/i915/skl: Program the DDB allocation
drm/i915/skl: Store the new WM state at the very end of the update
drm/i915/skl: Read back the DDB allocation hw state
drm/i915/skl: Augment the latency debugfs files for SKL
drm/i915/skl: Add a debugfs file to dump the DDB allocation
drm/i915/skl: Check the DDB state at modeset
drm/i915/skl: Make 'end' of the DDB allocation entry exclusive
drm/i915/skl: Use a more descriptive parameter name in skl_compute_plane_wm()
drm/i915/skl: Make res_blocks/lines intermediate values 32 bits
drm/i915/skl: Reduce the number of holes in struct skl_wm_level
drm/i915/skl: Move all the WM compute functions in one place
drm/i915/skl: Rework when the transition WMs are computed
drm/i915/skl: Correctly align skl_compute_plane_wm() arguments
drm/i915/skl: Reduce the indentation level in skl_write_wm_values()
drm/i915/skl: Stage the pipe DDB allocation
drm/i915/skl: Flush the WM configuration
drm/i915/skl: Log the order in which we flush the pipes in the WM code
Daniel Vetter (5):
drm/i915: Check pipe_config.has_dp_encoder instead of encoder types
drm/i915: Move pll state commit into intel_modeset_update_state
drm/i915/dp: Don't stop the link when retraining
drm/i915: Update DRIVER_DATE to 20141107
Merge remote-tracking branch 'airlied/drm-next' into HEAD
Dave Gordon (1):
drm/i915: Remove redundant return value and WARN_ON
Gustavo Padovan (6):
drm/i915: only flip frontbuffer if crtc is active
drm: make sure visible is set to false if fb is null
drm/i915: remove unneeded visible check
drm/i915: create a prepare step for primary planes updates
drm/i915: create a prepare phase for sprite plane updates
drm/i915: use intel_fb_obj() macros to assign gem objects
Jani Nikula (18):
drm/i915: add new intel audio file to group DP/HDMI audio
drm/i915/audio: constify hdmi audio clock struct
drm/i915/audio: beat some sense into the variable types and names
drm/i915: pass intel_encoder to intel_write_eld
drm/i915/audio: pass intel_encoder on to platform specific ELD functions
drm/i915/audio: set ELD Conn_Type at one place
drm/i915/ddi: write ELD where it's supposed to be done
drm/i915: introduce intel_audio_codec_{enable, disable}
drm/i915/audio: remove misleading checks for !eld[0]
drm/i915: clean up and clarify audio related register defines
drm/i915: rewrite hsw/bdw audio codec enable/disable sequences
drm/i915/audio: rewrite vlv/chv and gen 5-7 audio codec enable sequence
drm/i915/audio: add vlv/chv/gen5-7 audio codec disable sequence
drm/i915: enable audio codec after port
drm/i915/audio: add audio codec disable on g4x
drm/i915/audio: add audio codec enable debug log for g4x
drm/i915: make pipe/port based audio valid accessors easier to use
drm/i915/audio: add DOC comment describing HDA over HDMI/DP
John Harrison (2):
drm/i915: Fix null pointer dereference in ring cleanup code
drm/i915: Remove redundant parameter to i915_gem_object_wait_rendering__tail()
Mika Kuoppala (3):
drm/i915: Redefine WARN_ON to include the condition
Revert "drm/i915/vlv: Remove check for Old Ack during forcewake"
drm/i915: Add gen to the gpu hang ecode
Paulo Zanoni (5):
drm/i915: transform INTEL_OUTPUT_* into an enum
drm/i915: kill intel_resume_prepare()
drm/i915: run hsw_disable_pc8() later on resume
drm/i915: fix "Unexpected fault" error message line break
drm/i915: fix RPS on runtime suspend
Pradeep Bhat (5):
drm/i915/skl: Read the Memory Latency Values for WM computation
drm/i915/skl: Register definitions and macros for SKL Watermark regs
drm/i915/skl: Definition of SKL WM param structs for pipe/plane
drm/i915/skl: SKL Watermark Computation
drm/i915/skl: Read the pipe WM HW state
Sonika Jindal (1):
drm/i915: Update plane parameters for cursor plane (v2)
Thomas Daniel (1):
drm/i915/bdw: Setup global hardware status page in execlists mode
Tvrtko Ursulin (2):
drm/i915: Move flags describing VMA mappings into the VMA
drm/i915: Make intel_pin_and_fence_fb_obj take plane and framebuffer
Vandana Kannan (2):
drm/i915/gen9: Add 2us read latency to WM level
drm/i915/gen9: Disable WM if corresponding latency is 0
Ville Syrjälä (37):
drm/i915: Warn if trying to register eDP on port != B/C on vlv/chv
drm/i915: Remove high level intel_edp_vdd_{on, off}() from hpd/detect
drm/i915: Store power sequencer delays in intel_dp
drm/i915: Don't initialize power seqeuencer delays more than once
drm/i915: Split power sequencer panel on/off functions to locked and unlocked variants
drm/i915: Hold the pps mutex across the whole panel power enable sequence
drm/i915: Wait for PHY port ready before link training on VLV/CHV
drm/i915: Fix eDP link training when switching pipes on VLV/CHV
drm/i915: Kick the power sequencer before AUX transactions
drm/i915: Don't kick the power seqeuncer just to check if we have vdd/panel power
drm/i915: Clear PPS port select when giving up the power sequencer
drm/i915: Warn if stealing non pipe A/B power sequencer
drm/i915: Steal power sequencer in vlv_power_sequencer_pipe()
drm/i915: Improve VDD/PPS debugs
drm/i915: Warn if panel power is already on when enabling it
drm/i915: Warn if stealing power sequencer from an active eDP port
drm/i915: Make sure DPLL is enabled when kicking the power sequencer on VLV/CHV
drm/i915: Do vlv cmnlane toggle w/a in more cases
drm/i915: Initialize new chv primary plane and pipe blender registers
drm/i915: Add support for CHV pipe B sprite CSC
drm/i915: Enable pipe-a power well on chv
drm/i915: Initialize PPS timestamps on vlv/chv
drm/i915: Read out the power sequencer port assignment on resume on vlv/chv
drm/i915: Apply some ocd for IMR vs. IER order during irq enable
drm/i915: Use DPINVGTT_STATUS_MASK
drm/i915: Use gen8_gt_irq_reset() in cherryview_irq_uninstall()
drm/i915: Drop the extra GEN8_PCU_IIR posting read from cherryview_irq_preinstall()
drm/i915: Use a consistent order between IIR, IER, IMR writes on vlv/chv
drm/i915: Use GEN5_IRQ_RESET() on vlv/chv
drm/i915: Call gen5_gt_irq_reset() from valleyview_irq_uninstall()
drm/i915: Make valleyview_display_irqs_(un)install() work for chv
drm/i915: Refactor vlv_display_irq_reset()
drm/i914: Refactor vlv_display_irq_postinstall()
drm/i915: Drop useless VLV_IIR writes from vlv_display_irq_postinstall()
drm/i915: Kill leftover GTIIR writes from valleyview_irq_preinstall()
drm/i915: Move the .global_resources() hook call into modeset_update_crtc_power_domains()
drm/i915: Cache HPLL frequency on VLV/CHV
Zhe Wang (2):
drm/i915/skl: Gen9 Forcewake
drm/i915/skl: Enable Gen9 RC6
Documentation/DocBook/drm.tmpl | 5 +
drivers/gpu/drm/drm_plane_helper.c | 5 +
drivers/gpu/drm/i915/Makefile | 6 +-
drivers/gpu/drm/i915/i915_cmd_parser.c | 18 +-
drivers/gpu/drm/i915/i915_debugfs.c | 132 ++-
drivers/gpu/drm/i915/i915_drv.c | 75 +-
drivers/gpu/drm/i915/i915_drv.h | 105 ++-
drivers/gpu/drm/i915/i915_gem.c | 75 +-
drivers/gpu/drm/i915/i915_gem_context.c | 10 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 35 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 26 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 8 +-
drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +
drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
drivers/gpu/drm/i915/i915_gem_tiling.c | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 13 +-
drivers/gpu/drm/i915/i915_irq.c | 156 ++--
drivers/gpu/drm/i915/i915_reg.h | 303 +++++--
drivers/gpu/drm/i915/intel_audio.c | 462 ++++++++++
drivers/gpu/drm/i915/intel_ddi.c | 61 +-
drivers/gpu/drm/i915/intel_display.c | 1143 +++++++++++--------------
drivers/gpu/drm/i915/intel_dp.c | 429 ++++++----
drivers/gpu/drm/i915/intel_drv.h | 65 +-
drivers/gpu/drm/i915/intel_fbdev.c | 20 +-
drivers/gpu/drm/i915/intel_hdmi.c | 19 +-
drivers/gpu/drm/i915/intel_lrc.c | 52 +-
drivers/gpu/drm/i915/intel_pm.c | 1034 +++++++++++++++++++++-
drivers/gpu/drm/i915/intel_renderstate.h | 1 +
drivers/gpu/drm/i915/intel_renderstate_gen8.c | 802 +++++++++++++----
drivers/gpu/drm/i915/intel_renderstate_gen9.c | 974 +++++++++++++++++++++
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 20 +-
drivers/gpu/drm/i915/intel_sprite.c | 170 +++-
drivers/gpu/drm/i915/intel_uncore.c | 192 ++++-
include/uapi/drm/i915_drm.h | 6 +
35 files changed, 4970 insertions(+), 1464 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_audio.c
create mode 100644 drivers/gpu/drm/i915/intel_renderstate_gen9.c
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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