On Nov 13, 2014 3:20 AM, "Borislav Petkov" <bp@xxxxxxxxx> wrote: > > On Wed, Nov 12, 2014 at 07:14:21PM -0800, Andy Lutomirski wrote: > > On 11/11/2014 10:43 AM, Ross Zwisler wrote: > > > If clwb is available on the system, use it in drm_clflush_virt_range. > > > If clwb is not available, fall back to clflushopt if you can. > > > If clflushopt is not supported, fall all the way back to clflush. > > > > I don't know exactly what drm_clflush_virt_range (and the other > > functions you're modifying similarly) are for, but it seems plausible to > > me that they're used before reads to make sure that non-coherent memory > > sees updated data. If that's true, then this will break it. > > Why would it break it? The updated cachelines will be in memory and > subsequent reads will be serviced from the cache instead from going to > memory as it is not invalidated as it would be by CLFLUSH. > > /me is puzzled. Suppose you map some device memory WB, and then the device non-coherently updates. If you want the CPU to see it, you need clflush or clflushopt. Some architectures might do this for dma_sync_single_for_cpu with DMA_FROM_DEVICE. I'm not sure that such a thing exists on x86. --Andy _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
