Comment # 34
on bug 72785
from Luke-Jr
(In reply to Luke-Jr from comment #33) > Looks like clEnqueueNDRangeKernel is re-compiling (or at least optimising?) > the kernel, and taking a looooooooong time to do so. Isn't compiling > supposed to be done *once* by clBuildProgram? Also, seems it pisses off the hardware really bad when it finishes (although I only have a 5850 and 6xxx for testing at the moment): [ 855.257659] radeon 0000:01:00.0: ring 3 stalled for more than 10000msec [ 855.257670] radeon 0000:01:00.0: GPU lockup (waiting for 0x000000000000963c last fence id 0x000000000000963b on ring 3) [ 855.283709] dmar: DRHD: handling fault status reg 3 [ 855.283730] dmar: DMAR:[DMA Read] Request device [01:00.0] fault addr 401df000 DMAR:[fault reason 06] PTE Read access is not set [ 855.283734] radeon 0000:01:00.0: Saved 514 dwords of commands on ring 0. [ 855.283757] radeon 0000:01:00.0: GPU softreset: 0x0000000D [ 855.283762] radeon 0000:01:00.0: GRBM_STATUS = 0xB0433828 [ 855.283766] radeon 0000:01:00.0: GRBM_STATUS_SE0 = 0x08000007 [ 855.283770] radeon 0000:01:00.0: GRBM_STATUS_SE1 = 0x00000007 [ 855.283773] radeon 0000:01:00.0: SRBM_STATUS = 0x200000C0 [ 855.283776] radeon 0000:01:00.0: SRBM_STATUS2 = 0x00000000 [ 855.283779] radeon 0000:01:00.0: R_008674_CP_STALLED_STAT1 = 0x00000000 [ 855.283783] radeon 0000:01:00.0: R_008678_CP_STALLED_STAT2 = 0x400C0000 [ 855.283799] radeon 0000:01:00.0: R_00867C_CP_BUSY_STAT = 0x00050002 [ 855.283803] radeon 0000:01:00.0: R_008680_CP_STAT = 0x80268647 [ 855.283813] radeon 0000:01:00.0: R_00D034_DMA_STATUS_REG = 0x44483146 [ 855.298675] radeon 0000:01:00.0: GRBM_SOFT_RESET=0x00007F6B [ 855.298731] radeon 0000:01:00.0: SRBM_SOFT_RESET=0x00100100 [ 855.299894] radeon 0000:01:00.0: GRBM_STATUS = 0x00003828 [ 855.299898] radeon 0000:01:00.0: GRBM_STATUS_SE0 = 0x00000007 [ 855.299901] radeon 0000:01:00.0: GRBM_STATUS_SE1 = 0x00000007 [ 855.299904] radeon 0000:01:00.0: SRBM_STATUS = 0x200000C0 [ 855.299908] radeon 0000:01:00.0: SRBM_STATUS2 = 0x00000000 [ 855.299911] radeon 0000:01:00.0: R_008674_CP_STALLED_STAT1 = 0x00000000 [ 855.299914] radeon 0000:01:00.0: R_008678_CP_STALLED_STAT2 = 0x00000000 [ 855.299918] radeon 0000:01:00.0: R_00867C_CP_BUSY_STAT = 0x00000000 [ 855.299921] radeon 0000:01:00.0: R_008680_CP_STAT = 0x00000000 [ 855.299924] radeon 0000:01:00.0: R_00D034_DMA_STATUS_REG = 0x44C83D57 [ 855.299956] radeon 0000:01:00.0: GPU reset succeeded, trying to resume [ 855.322535] [drm] enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0 [ 855.323757] [drm] PCIE GART of 1024M enabled (table at 0x0000000000273000). [ 855.323855] radeon 0000:01:00.0: WB enabled [ 855.323859] radeon 0000:01:00.0: fence driver on ring 0 use gpu addr 0x0000000040000c00 and cpu addr 0xffff8800a7056c00 [ 855.323862] radeon 0000:01:00.0: fence driver on ring 3 use gpu addr 0x0000000040000c0c and cpu addr 0xffff8800a7056c0c [ 855.325391] radeon 0000:01:00.0: fence driver on ring 5 use gpu addr 0x0000000000072118 and cpu addr 0xffffc900052b2118 [ 855.341736] [drm] ring test on 0 succeeded in 3 usecs [ 855.341750] [drm] ring test on 3 succeeded in 1 usecs [ 855.519119] [drm] ring test on 5 succeeded in 2 usecs [ 855.519135] [drm] UVD initialized successfully. [ 855.523058] [drm] ib test on ring 0 succeeded in 0 usecs [ 855.523143] [drm] ib test on ring 3 succeeded in 1 usecs [ 855.675747] [drm] ib test on ring 5 succeeded
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