This patch changes signal names in struct ipu_di_signal_cfg
as per the industry standard names, and renames fields that
were using CamelCase.
Signed-off-by: Deepak Das <deepak_das@xxxxxxxxxx>
Signed-off-by: Steve Longerbeam <steve_longerbeam@xxxxxxxxxx>
---
drivers/gpu/ipu-v3/ipu-di.c | 68 +++++++++++++++++-----------------
drivers/staging/imx-drm/ipuv3-crtc.c | 16 ++++----
include/video/imx-ipu-v3.h | 16 ++++----
3 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index 47615ce..b306f07 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -207,10 +207,10 @@ static void ipu_di_sync_config(struct ipu_di *di, struct di_sync_config *config,
static void ipu_di_sync_config_interlaced(struct ipu_di *di,
struct ipu_di_signal_cfg *sig)
{
- u32 h_total = sig->width + sig->h_sync_width +
- sig->h_start_width + sig->h_end_width;
- u32 v_total = sig->height + sig->v_sync_width +
- sig->v_start_width + sig->v_end_width;
+ u32 h_total = sig->width + sig->h_sync_len +
+ sig->h_back_porch + sig->h_front_porch;
+ u32 v_total = sig->height + sig->v_sync_len +
+ sig->v_back_porch + sig->v_front_porch;
u32 reg;
struct di_sync_config cfg[] = {
{
@@ -229,7 +229,7 @@ static void ipu_di_sync_config_interlaced(struct ipu_di *di,
}, {
.run_count = v_total / 2 - 1,
.run_src = DI_SYNC_HSYNC,
- .offset_count = sig->v_start_width,
+ .offset_count = sig->v_back_porch,
.offset_src = DI_SYNC_HSYNC,
.repeat_count = 2,
.cnt_clr_src = DI_SYNC_VSYNC,
@@ -249,7 +249,7 @@ static void ipu_di_sync_config_interlaced(struct ipu_di *di,
.cnt_clr_src = DI_SYNC_VSYNC,
}, {
.run_src = DI_SYNC_CLK,
- .offset_count = sig->h_start_width,
+ .offset_count = sig->h_back_porch,
.offset_src = DI_SYNC_CLK,
.repeat_count = sig->width,
.cnt_clr_src = 5,
@@ -277,10 +277,10 @@ static void ipu_di_sync_config_interlaced(struct ipu_di *di,
static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
struct ipu_di_signal_cfg *sig, int div)
{
- u32 h_total = sig->width + sig->h_sync_width + sig->h_start_width +
- sig->h_end_width;
- u32 v_total = sig->height + sig->v_sync_width + sig->v_start_width +
- sig->v_end_width;
+ u32 h_total = sig->width + sig->h_sync_len + sig->h_back_porch +
+ sig->h_front_porch;
+ u32 v_total = sig->height + sig->v_sync_len + sig->v_back_porch +
+ sig->v_front_porch;
struct di_sync_config cfg[] = {
{
/* 1: INT_HSYNC */
@@ -294,25 +294,25 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
.offset_src = DI_SYNC_CLK,
.cnt_polarity_gen_en = 1,
.cnt_polarity_trigger_src = DI_SYNC_CLK,
- .cnt_down = sig->h_sync_width * 2,
+ .cnt_down = sig->h_sync_len * 2,
} , {
/* PIN3: VSYNC */
.run_count = v_total - 1,
.run_src = DI_SYNC_INT_HSYNC,
.cnt_polarity_gen_en = 1,
.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
- .cnt_down = sig->v_sync_width * 2,
+ .cnt_down = sig->v_sync_len * 2,
} , {
/* 4: Line Active */
.run_src = DI_SYNC_HSYNC,
- .offset_count = sig->v_sync_width + sig->v_start_width,
+ .offset_count = sig->v_sync_len + sig->v_back_porch,
.offset_src = DI_SYNC_HSYNC,
.repeat_count = sig->height,
.cnt_clr_src = DI_SYNC_VSYNC,
} , {
/* 5: Pixel Active, referenced by DC */
.run_src = DI_SYNC_CLK,
- .offset_count = sig->h_sync_width + sig->h_start_width,
+ .offset_count = sig->h_sync_len + sig->h_back_porch,
.offset_src = DI_SYNC_CLK,
.repeat_count = sig->width,
.cnt_clr_src = 5, /* Line Active */
@@ -339,7 +339,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
} , {
/* 3: Line Active */
.run_src = DI_SYNC_INT_HSYNC,
- .offset_count = sig->v_sync_width + sig->v_start_width,
+ .offset_count = sig->v_sync_len + sig->v_back_porch,
.offset_src = DI_SYNC_INT_HSYNC,
.repeat_count = sig->height,
.cnt_clr_src = 3 /* VSYNC */,
@@ -351,11 +351,11 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
.offset_src = DI_SYNC_CLK,
.cnt_polarity_gen_en = 1,
.cnt_polarity_trigger_src = DI_SYNC_CLK,
- .cnt_down = sig->h_sync_width * 2,
+ .cnt_down = sig->h_sync_len * 2,
} , {
/* 5: Pixel Active signal to DC */
.run_src = DI_SYNC_CLK,
- .offset_count = sig->h_sync_width + sig->h_start_width,
+ .offset_count = sig->h_sync_len + sig->h_back_porch,
.offset_src = DI_SYNC_CLK,
.repeat_count = sig->width,
.cnt_clr_src = 4, /* Line Active */
@@ -367,7 +367,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
.offset_src = DI_SYNC_INT_HSYNC,
.cnt_polarity_gen_en = 1,
.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
- .cnt_down = sig->v_sync_width * 2,
+ .cnt_down = sig->v_sync_len * 2,
} , {
/* PIN4: HSYNC for VGA via TVEv2 on i.MX53-QSB */
.run_count = h_total - 1,
@@ -376,7 +376,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
.offset_src = DI_SYNC_CLK,
.cnt_polarity_gen_en = 1,
.cnt_polarity_trigger_src = DI_SYNC_CLK,
- .cnt_down = sig->h_sync_width * 2,
+ .cnt_down = sig->h_sync_len * 2,
} , {
/* PIN6: VSYNC for VGA via TVEv2 on i.MX53-QSB */
.run_count = v_total - 1,
@@ -385,7 +385,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
.offset_src = DI_SYNC_INT_HSYNC,
.cnt_polarity_gen_en = 1,
.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
- .cnt_down = sig->v_sync_width * 2,
+ .cnt_down = sig->v_sync_len * 2,
} , {
/* unused */
},
@@ -522,15 +522,15 @@ static void ipu_di_config_clock(struct ipu_di *di,
static void adapt_panel_to_ipu_restricitions(struct ipu_di *di,
struct ipu_di_signal_cfg *sig)
{
- if (sig->v_end_width < 2) {
- uint16_t diff = 2 - sig->v_end_width;
-
- if (sig->v_start_width >= diff) {
- sig->v_end_width = 2;
- sig->v_start_width -= diff;
- } else if (sig->v_sync_width > diff) {
- sig->v_end_width = 2;
- sig->v_sync_width = sig->v_sync_width - diff;
+ if (sig->v_front_porch < 2) {
+ uint16_t diff = 2 - sig->v_front_porch;
+
+ if (sig->v_back_porch >= diff) {
+ sig->v_front_porch = 2;
+ sig->v_back_porch -= diff;
+ } else if (sig->v_sync_len > diff) {
+ sig->v_front_porch = 2;
+ sig->v_sync_len = sig->v_sync_len - diff;
} else
dev_warn(di->ipu->dev,
"di%d: failed to adapt timing\n", di->id);
@@ -550,7 +550,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
dev_dbg(di->ipu->dev, "di%d: panel size = %d x %d\n",
di->id, sig->width, sig->height);
- if ((sig->v_sync_width == 0) || (sig->h_sync_width == 0))
+ if ((sig->v_sync_len == 0) || (sig->h_sync_len == 0))
return -EINVAL;
adapt_panel_to_ipu_restricitions(di, sig);
@@ -589,9 +589,9 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
vsync_cnt = 7;
- if (sig->Hsync_pol)
+ if (sig->hsync_pol)
di_gen |= DI_GEN_POLARITY_3;
- if (sig->Vsync_pol)
+ if (sig->vsync_pol)
di_gen |= DI_GEN_POLARITY_2;
} else {
ipu_di_sync_config_noninterlaced(di, sig, div);
@@ -605,7 +605,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
vsync_cnt = 6;
- if (sig->Hsync_pol) {
+ if (sig->hsync_pol) {
if (sig->hsync_pin == 2)
di_gen |= DI_GEN_POLARITY_2;
else if (sig->hsync_pin == 4)
@@ -613,7 +613,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
else if (sig->hsync_pin == 7)
di_gen |= DI_GEN_POLARITY_7;
}
- if (sig->Vsync_pol) {
+ if (sig->vsync_pol) {
if (sig->vsync_pin == 3)
di_gen |= DI_GEN_POLARITY_3;
else if (sig->vsync_pin == 6)
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index be24cb9..8b4440a 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -159,22 +159,22 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
sig_cfg.interlaced = 1;
if (mode->flags & DRM_MODE_FLAG_PHSYNC)
- sig_cfg.Hsync_pol = 1;
+ sig_cfg.hsync_pol = 1;
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
- sig_cfg.Vsync_pol = 1;
+ sig_cfg.vsync_pol = 1;
sig_cfg.enable_pol = 1;
sig_cfg.clk_pol = 0;
sig_cfg.width = mode->hdisplay;
sig_cfg.height = mode->vdisplay;
sig_cfg.pixel_fmt = out_pixel_fmt;
- sig_cfg.h_start_width = mode->htotal - mode->hsync_end;
- sig_cfg.h_sync_width = mode->hsync_end - mode->hsync_start;
- sig_cfg.h_end_width = mode->hsync_start - mode->hdisplay;
+ sig_cfg.h_back_porch = mode->htotal - mode->hsync_end;
+ sig_cfg.h_sync_len = mode->hsync_end - mode->hsync_start;
+ sig_cfg.h_front_porch = mode->hsync_start - mode->hdisplay;
- sig_cfg.v_start_width = mode->vtotal - mode->vsync_end;
- sig_cfg.v_sync_width = mode->vsync_end - mode->vsync_start;
- sig_cfg.v_end_width = mode->vsync_start - mode->vdisplay;
+ sig_cfg.v_back_porch = mode->vtotal - mode->vsync_end;
+ sig_cfg.v_sync_len = mode->vsync_end - mode->vsync_start;
+ sig_cfg.v_front_porch = mode->vsync_start - mode->vdisplay;
sig_cfg.pixelclock = mode->clock * 1000;
sig_cfg.clkflags = ipu_crtc->di_clkflags;
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index d2f621d..7e1bc61 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -40,18 +40,18 @@ struct ipu_di_signal_cfg {
unsigned data_pol:1; /* true = inverted */
unsigned clk_pol:1; /* true = rising edge */
unsigned enable_pol:1;
- unsigned Hsync_pol:1; /* true = active high */
- unsigned Vsync_pol:1;
+ unsigned hsync_pol:1; /* true = active high */
+ unsigned vsync_pol:1;
u16 width;
u16 height;
u32 pixel_fmt;
- u16 h_start_width;
- u16 h_sync_width;
- u16 h_end_width;
- u16 v_start_width;
- u16 v_sync_width;
- u16 v_end_width;
+ u16 h_back_porch;
+ u16 h_sync_len;
+ u16 h_front_porch;
+ u16 v_back_porch;
+ u16 v_sync_len;
+ u16 v_front_porch;
u32 v_to_h_sync;
unsigned long pixelclock;
#define IPU_DI_CLKMODE_SYNC (1 << 0)
--
1.7.9.5
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