Previously, pixel clock polarity was hardcoded and wasn't configurable. This patch adds support to configure the pixel clock polarity from the DRM mode flags. Signed-off-by: Mohsin Kazmi <mohsin_kazmi@xxxxxxxxxx> Signed-off-by: Steve Longerbeam <steve_longerbeam@xxxxxxxxxx> --- drivers/staging/imx-drm/ipuv3-crtc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c index 316e5bf..65fe429 100644 --- a/drivers/staging/imx-drm/ipuv3-crtc.c +++ b/drivers/staging/imx-drm/ipuv3-crtc.c @@ -291,9 +291,10 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, sig_cfg.hsync_pol = 1; if (mode->flags & DRM_MODE_FLAG_PVSYNC) sig_cfg.vsync_pol = 1; + if (mode->flags & DRM_MODE_FLAG_PCLK) + sig_cfg.clk_pol = 1; sig_cfg.enable_pol = 1; - sig_cfg.clk_pol = 0; sig_cfg.width = mode->hdisplay; sig_cfg.height = mode->vdisplay; sig_cfg.pixel_fmt = out_pixel_fmt; -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
