Comment # 2
on bug 85596
from Vadim Girlin
(In reply to Lauri Kasanen from comment #0) > Many big shaders that currently fail with > r600_shader_select - Failed to build shader variant (type=1) -12 > r600_shader_from_tgsi - GPR limit exceeded - shader requires foo registers > > would actually work if the GPR check was moved to after SB, as SB reduces > the GPR usage quite nicely. > > Another thing is that 128 is the lowest common denominator, and many cards > have 192 or 256, which could be checked with the radeon_info ioctl. As Alex said, ISA encoding doesn't allow to address more than 128 registers in the instructions. IIRC we also by default reserve 4 GPRs as temporary (they are not preserved between ALU clauses), so the actual limit is 124 (or even 120?). It's also the reason why we can't simply move the GPR check, the shader is passed from TGSI translator to SB in the ISA encoding which can't represent the code that uses more than 128 registers. If anyone would like to revive a direct TGSI->SB translator that solves the problem, here is the branch: http://cgit.freedesktop.org/~vadimg/mesa/log/?h=wip-sb-tgsi There were no piglit regressions with that branch on evergreen when it was implemented, but now I suspect it's a bit outdated.
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