On Fri, Oct 10, 2014 at 12:00 PM, Alex Deucher <alexdeucher@xxxxxxxxx> wrote:
> On Thu, Oct 9, 2014 at 3:10 PM, Alexander Fyodorov <halcy@xxxxxxxxx> wrote:
>> 09.10.2014, 22:32, "Christian König" <christian.koenig@xxxxxxx>:
>>> Am 09.10.2014 um 20:15 schrieb Alexander Fyodorov:
>>>> 09.10.2014, 21:42, "Christian König" <christian.koenig@xxxxxxx>:
>>>>> For VRAM it is true that we have a couple of different caches between
>>>>> the CPU and the actually memory, which need to be flushed explicitly if
>>>>> you want to see a value written by the GPU.
>>>> Then maybe such a flush is what I need. How do I put it in the instruction ring buffer?
>>>
>>> At least we need to flush the HDP, but what hardware generation is this
>>> exactly? Some R6xx don't support hardware flushes in the ring buffer.
>>
>> I observed the problem on HD2400 and HD6670.
>>
>>> Try to call r600_mmio_hdp_flush(rdev) from the loop which checks the
>>> value written.
>>
>> Yep, it helped. Here is the patch against 3.10.53, tested on HD2400.
>>
>>
>> Flush VRAM cache before each read when polling.
>>
>> Signed-off-by: Alexander Fyodorov <halcy at yandex.ru>
>>
>>
>> Index: drivers/gpu/drm/radeon/r600.c
>> ===================================================================
>> --- drivers/gpu/drm/radeon/r600.c (revision 11647)
>> +++ drivers/gpu/drm/radeon/r600.c (working copy)
>> @@ -2899,6 +2899,7 @@
>> radeon_ring_unlock_commit(rdev, ring);
>>
>> for (i = 0; i < rdev->usec_timeout; i++) {
>> + r600_ioctl_wait_idle(rdev, rdev->vram_scratch.robj);
>> tmp = readl(ptr);
>> if (tmp == 0xDEADBEEF)
>> break;
>
> I think I'd prefer to just switch the test to use gart memory since
> this code is shared by different asics thay may not all implement hdp
> flush the same way. We can just reserve a couple of slots in the wb
> page.
Also newer versions of the test will need a similar fix.
Alex
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