Re: [PATCH 1/2] drm/radeon: Only enable and handle pageflip interrupts when needed

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Am 26.06.2014 12:39, schrieb Christian König:

Am 26.06.2014 11:29, schrieb Michel Dänzer:

From: Michel Dänzer <michel.daenzer@xxxxxxx>

Prevents radeon_crtc_handle_flip() from running before
radeon_flip_work_func(), resulting in a kernel panic due to the BUG_ON() 
in drm_vblank_put().

Tested-by: Dieter Nützel <Dieter@xxxxxxxxxxxxx>
Signed-off-by: Michel Dänzer <michel.daenzer@xxxxxxx>


Does patch #2 alone fixes the problem as well?


With #2 alone I get this during boot up (before plymouth):

[   11.942342] [drm] fb depth is 24
[   11.942344] [drm]    pitch is 7680
[   11.942739] fbcon: radeondrmfb (fb0) is primary device
[ 11.943090] [drm:radeon_crtc_handle_flip] *ERROR* radeon_crtc->flip_status = 0 != RADEON_FLIP_SUBMITTED(2) 
[   11.943912] Console: switching to colour frame buffer device 240x67
[   11.995623] radeon 0000:01:00.0: fb0: radeondrmfb frame buffer device
[   11.995628] radeon 0000:01:00.0: registered panic notifier
[ 11.998112] [drm] Initialized radeon 2.39.0 20080528 for 0000:01:00.0 on minor 0 [ 15.259867] [drm:radeon_crtc_handle_flip] *ERROR* radeon_crtc->flip_status = 0 != RADEON_FLIP_SUBMITTED(2) 

And during X / KDE start, again:
[ 30.960442] [drm:radeon_crtc_handle_flip] *ERROR* radeon_crtc->flip_status = 0 != RADEON_FLIP_SUBMITTED(2) [ 31.343925] [drm:radeon_crtc_handle_flip] *ERROR* radeon_crtc->flip_status = 0 != RADEON_FLIP_SUBMITTED(2) [ 37.687138] [drm:radeon_crtc_handle_flip] *ERROR* radeon_crtc->flip_status = 0 != RADEON_FLIP_SUBMITTED(2) [ 187.005621] [drm:radeon_crtc_handle_flip] *ERROR* radeon_crtc->flip_status = 0 != RADEON_FLIP_SUBMITTED(2) 

Much more in dmesg.
(See dmesg-3.16-rc2-Michel-2.xz)

But with Michel's #1+2 and 3 I got this in Xorg.0.log:
(See Xorg.0.log.old.xz)
(EE) [mi] EQ overflowing. Additional events will be discarded until existing events are processed. 
(EE)
(EE) Backtrace:


I would rather want to avoid turning the pflip interrupt on and off.


I'm under the impression, that #2 alone is more responsive, but.

Sorry, after Fußball ;-)

Dieter


---
  drivers/gpu/drm/radeon/cik.c       | 18 ++++++++++--------
  drivers/gpu/drm/radeon/evergreen.c | 18 ++++++++++--------
  drivers/gpu/drm/radeon/r600.c      | 12 ++++++++----
  drivers/gpu/drm/radeon/si.c        | 18 ++++++++++--------
  4 files changed, 38 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c 
index 0f4b38f..7f522a4 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -7145,21 +7145,21 @@ int cik_irq_set(struct radeon_device *rdev)
    	if (rdev->num_crtc >= 2) {
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[0]) ? GRPH_PFLIP_INT_MASK : 0);
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[1]) ? GRPH_PFLIP_INT_MASK : 0);
  	}
  	if (rdev->num_crtc >= 4) {
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[2]) ? GRPH_PFLIP_INT_MASK : 0);
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[3]) ? GRPH_PFLIP_INT_MASK : 0);
  	}
  	if (rdev->num_crtc >= 6) {
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[4]) ? GRPH_PFLIP_INT_MASK : 0);
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[5]) ? GRPH_PFLIP_INT_MASK : 0);
  	}
    	WREG32(DC_HPD1_INT_CONTROL, hpd1);
@@ -7611,8 +7611,10 @@ restart_ih:
  		case 14: /* D4 page flip */
  		case 16: /* D5 page flip */
  		case 18: /* D6 page flip */
-			DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
-			radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
+			src_id = (src_id - 8) >> 1;
+			DRM_DEBUG("IH: D%d flip\n", src_id + 1);
+			if (atomic_read(&rdev->irq.pflip[src_id]))
+				radeon_crtc_handle_flip(rdev, src_id);
  			break;
  		case 42: /* HPD hotplug */
  			switch (src_data) {
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c 
index 0443183..fa6e320 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4542,20 +4542,20 @@ int evergreen_irq_set(struct radeon_device *rdev) 
  	}
    	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
-	       GRPH_PFLIP_INT_MASK);
+	       atomic_read(&rdev->irq.pflip[0]) ? GRPH_PFLIP_INT_MASK : 0);
  	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
-	       GRPH_PFLIP_INT_MASK);
+	       atomic_read(&rdev->irq.pflip[1]) ? GRPH_PFLIP_INT_MASK : 0);
  	if (rdev->num_crtc >= 4) {
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[2]) ? GRPH_PFLIP_INT_MASK : 0);
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[3]) ? GRPH_PFLIP_INT_MASK : 0);
  	}
  	if (rdev->num_crtc >= 6) {
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[4]) ? GRPH_PFLIP_INT_MASK : 0);
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[5]) ? GRPH_PFLIP_INT_MASK : 0);
  	}
    	WREG32(DC_HPD1_INT_CONTROL, hpd1);
@@ -4950,8 +4950,10 @@ restart_ih:
  		case 14: /* D4 page flip */
  		case 16: /* D5 page flip */
  		case 18: /* D6 page flip */
-			DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
-			radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
+			src_id = (src_id - 8) >> 1;
+			DRM_DEBUG("IH: D%d flip\n", src_id + 1);
+			if (atomic_read(&rdev->irq.pflip[src_id]))
+				radeon_crtc_handle_flip(rdev, src_id);
  			break;
  		case 42: /* HPD hotplug */
  			switch (src_data) {
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c 
index ae54f76..2f9a2af 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3614,8 +3614,10 @@ int r600_irq_set(struct radeon_device *rdev)
  	WREG32(CP_INT_CNTL, cp_int_cntl);
  	WREG32(DMA_CNTL, dma_cntl);
  	WREG32(DxMODE_INT_MASK, mode_int);
-	WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
-	WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
+	WREG32(D1GRPH_INTERRUPT_CONTROL,
+ atomic_read(&rdev->irq.pflip[0]) ? DxGRPH_PFLIP_INT_MASK : 0); 
+	WREG32(D2GRPH_INTERRUPT_CONTROL,
+ atomic_read(&rdev->irq.pflip[1]) ? DxGRPH_PFLIP_INT_MASK : 0); 
  	WREG32(GRBM_INT_CNTL, grbm_int_cntl);
  	if (ASIC_IS_DCE3(rdev)) {
  		WREG32(DC_HPD1_INT_CONTROL, hpd1);
@@ -3920,11 +3922,13 @@ restart_ih:
  			break;
  		case 9: /* D1 pflip */
  			DRM_DEBUG("IH: D1 flip\n");
-			radeon_crtc_handle_flip(rdev, 0);
+			if (atomic_read(&rdev->irq.pflip[0]))
+				radeon_crtc_handle_flip(rdev, 0);
  			break;
  		case 11: /* D2 pflip */
  			DRM_DEBUG("IH: D2 flip\n");
-			radeon_crtc_handle_flip(rdev, 1);
+			if (atomic_read(&rdev->irq.pflip[1]))
+				radeon_crtc_handle_flip(rdev, 1);
  			break;
  		case 19: /* HPD/DAC hotplug */
  			switch (src_data) {
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index c128bde..5d37ea5 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -5919,21 +5919,21 @@ int si_irq_set(struct radeon_device *rdev)
    	if (rdev->num_crtc >= 2) {
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[0]) ? GRPH_PFLIP_INT_MASK : 0);
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[1]) ? GRPH_PFLIP_INT_MASK : 0);
  	}
  	if (rdev->num_crtc >= 4) {
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[2]) ? GRPH_PFLIP_INT_MASK : 0);
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[3]) ? GRPH_PFLIP_INT_MASK : 0);
  	}
  	if (rdev->num_crtc >= 6) {
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[4]) ? GRPH_PFLIP_INT_MASK : 0);
  		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
-		       GRPH_PFLIP_INT_MASK);
+		       atomic_read(&rdev->irq.pflip[5]) ? GRPH_PFLIP_INT_MASK : 0);
  	}
    	if (!ASIC_IS_NODCE(rdev)) {
@@ -6303,8 +6303,10 @@ restart_ih:
  		case 14: /* D4 page flip */
  		case 16: /* D5 page flip */
  		case 18: /* D6 page flip */
-			DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
-			radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
+			src_id = (src_id - 8) >> 1;
+			DRM_DEBUG("IH: D%d flip\n", src_id + 1);
+			if (atomic_read(&rdev->irq.pflip[src_id]))
+				radeon_crtc_handle_flip(rdev, src_id);
  			break;
  		case 42: /* HPD hotplug */
  			switch (src_data) {


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