Define the HLCDC (High LCD Controller) IP available on some sama5d3 SoCs (i.e. sama5d31, sama5d33, sama5d34 and sama5d36). Signed-off-by: Boris BREZILLON <boris.brezillon@xxxxxxxxxxxxxxxxxx> --- arch/arm/boot/dts/sama5d3_lcd.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi index 2186b89..02a7012 100644 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi @@ -116,6 +116,32 @@ }; }; + hlcdc: hlcdc@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-dc"; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default", "rgb-444", "rgb-565", "rgb-666", "rgb-888"; + pinctrl-0 = <&pinctrl_lcd_base>; + pinctrl-1 = <&pinctrl_lcd_base &pinctrl_lcd_rgb444>; + pinctrl-2 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>; + pinctrl-3 = <&pinctrl_lcd_base &pinctrl_lcd_rgb666>; + pinctrl-4 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + pmc: pmc@fffffc00 { periphck { lcdc_clk: lcdc_clk { -- 1.8.3.2 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel