Hi Dave ! So your AST driver in -next is blowing up on my power8 box :-) There are several issues that I want to discuss here (YC Chen on CC might also have some valuable input here). * First, accessors. The first obvious cause for blowing up for me is that you are using the "old style" PIO offsets for these guys: #define AST_IO_AR_PORT_WRITE (0x40) #define AST_IO_MISC_PORT_WRITE (0x42) #define AST_IO_SEQ_PORT (0x44) #define AST_DAC_INDEX_READ (0x3c7) #define AST_IO_DAC_INDEX_WRITE (0x48) #define AST_IO_DAC_DATA (0x49) #define AST_IO_GR_PORT (0x4E) #define AST_IO_CRTC_PORT (0x54) #define AST_IO_INPUT_STATUS1_READ (0x5A) #define AST_IO_MISC_PORT_READ (0x4C) (And accessing them via PIO) And I don't have PIO on that platform at all :-) I tried using MMIO, but the above offsets don't work. Those things are accessible via the MMIO BAR which is much better via these offsets: #define AR_PORT_WRITE (pAST->MMIOVirtualAddr + 0x3c0) #define MISC_PORT_WRITE (pAST->MMIOVirtualAddr + 0x3c2) #define VGA_ENABLE_PORT (pAST->MMIOVirtualAddr + 0x3c3) #define SEQ_PORT (pAST->MMIOVirtualAddr + 0x3c4) #define DAC_INDEX_READ (pAST->MMIOVirtualAddr + 0x3c7) #define DAC_INDEX_WRITE (pAST->MMIOVirtualAddr + 0x3c8) #define DAC_DATA (pAST->MMIOVirtualAddr + 0x3c9) #define GR_PORT (pAST->MMIOVirtualAddr + 0x3cE) #define CRTC_PORT (pAST->MMIOVirtualAddr + 0x3d4) #define INPUT_STATUS1_READ (pAST->MMIOVirtualAddr + 0x3dA) #define MISC_PORT_READ (pAST->MMIOVirtualAddr + 0x3cc) (From the X driver). The spec is pretty tricky to read but seems to indicate that the above offset should also work for PIO if needed, however, it seems like the X driver is pretty happy to use MMIO unconditionally for them. Any objection on me sending you a patch to send (almost) everybody to use the MMIO path ? The only remaining "issues" with PIO is the EnableVGA / IsVGAEnabled path which still uses PIO in X. Now, at least on the AST2400, the register in question is also on MMIO (3c3, aka VGA_ENABLE_PORT in the above list), but I don't know whether that works on all the older chipsets. (YC Chen on CC might have an opinion). * Then, I notice that you only POST the chip in the "thaw" path which as far as I can tell is only called on resume from sleep, am I correct ? We don't have a BIOS so we rely on the kernel driver doing the full init. For example we come up with VGA disabled, so the driver must enable it (via 3c3 MMIO !) first thing first. The current probe code will just blow up even if adjusted to use the MMIO offsets due to trying to access the CRTC registers when VGA is disabled. This leads to the question, mostly for YC Chen I suppose: Is there a way to detect that the chip has been POSTed already by the BIOS or not ? Should we key that off VGA Enabled being 0 ? Cheers, Ben. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
