Comment # 54
on bug 78453
from vincent
Content of radeon_fence_info in this case is : --- ring 0 --- Last signaled fence 0x0000000000000002 Last emitted 0x0000000000000003 Last sync to ring 1 0x0000000000000000 Last sync to ring 2 0x0000000000000000 Last sync to ring 3 0x0000000000000000 Last sync to ring 4 0x0000000000000000 Last sync to ring 5 0x0000000000000000 --- ring 1 --- Last signaled fence 0x0000000000000003 Last emitted 0x0000000000000003 Last sync to ring 0 0x0000000000000000 Last sync to ring 2 0x0000000000000000 Last sync to ring 3 0x0000000000000000 Last sync to ring 4 0x0000000000000000 Last sync to ring 5 0x0000000000000000 --- ring 2 --- Last signaled fence 0x0000000000000001 Last emitted 0x0000000000000001 Last sync to ring 0 0x0000000000000000 Last sync to ring 1 0x0000000000000000 Last sync to ring 3 0x0000000000000000 Last sync to ring 4 0x0000000000000000 Last sync to ring 5 0x0000000000000000 --- ring 3 --- Last signaled fence 0x00000000000007f7 Last emitted 0x00000000000007f7 Last sync to ring 0 0x0000000000000000 Last sync to ring 1 0x0000000000000000 Last sync to ring 2 0x0000000000000000 Last sync to ring 4 0x0000000000000000 Last sync to ring 5 0x0000000000000000 --- ring 4 --- Last signaled fence 0x0000000000000001 Last emitted 0x0000000000000001 Last sync to ring 0 0x0000000000000000 Last sync to ring 1 0x0000000000000000 Last sync to ring 2 0x0000000000000000 Last sync to ring 3 0x0000000000000000 Last sync to ring 5 0x0000000000000000 --- ring 5 --- Last signaled fence 0x0000000000000002 Last emitted 0x0000000000000002 Last sync to ring 0 0x0000000000000000 Last sync to ring 1 0x0000000000000000 Last sync to ring 2 0x0000000000000000 Last sync to ring 3 0x0000000000000000 Last sync to ring 4 0x0000000000000000 I can't run eglinfo in this case so I think it's expected that ring 0 does not attempt to sync with ring 3. I don't know if dmesg attached in #53 is enough to determine why the dma engine is stalling.
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