On Wed, May 7, 2014 at 4:44 AM, Jingoo Han <jg1.han@xxxxxxxxxxx> wrote:
> Use DPCD defines of drm_dp_helper.h; thus, duplicated DPCD defines
> of exynos_dp_core.h can be removed. Also, DP_TEST_EDID_CHECKSUM
> define is added to drm_dp_helper.h. There is no functional change.
>
> Signed-off-by: Jingoo Han <jg1.han@xxxxxxxxxxx>
This is a nice improvement.
Reviewed-by: Sean Paul <seanpaul@xxxxxxxxxxxx>
> ---
> drivers/gpu/drm/exynos/exynos_dp_core.c | 98 +++++++++++++++----------------
> drivers/gpu/drm/exynos/exynos_dp_core.h | 59 ++-----------------
> include/drm/drm_dp_helper.h | 2 +
> 3 files changed, 55 insertions(+), 104 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
> index 64b2dd8..92cfbb3 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
> @@ -141,15 +141,15 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
> return -EIO;
> }
>
> - exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
> + exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
> &test_vector);
> - if (test_vector & DPCD_TEST_EDID_READ) {
> + if (test_vector & DP_TEST_LINK_EDID_READ) {
> exynos_dp_write_byte_to_dpcd(dp,
> - DPCD_ADDR_TEST_EDID_CHECKSUM,
> + DP_TEST_EDID_CHECKSUM,
> edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
> exynos_dp_write_byte_to_dpcd(dp,
> - DPCD_ADDR_TEST_RESPONSE,
> - DPCD_TEST_EDID_CHECKSUM_WRITE);
> + DP_TEST_RESPONSE,
> + DP_TEST_EDID_CHECKSUM_WRITE);
> }
> } else {
> dev_info(dp->dev, "EDID data does not include any extensions.\n");
> @@ -171,15 +171,15 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
> }
>
> exynos_dp_read_byte_from_dpcd(dp,
> - DPCD_ADDR_TEST_REQUEST,
> + DP_TEST_REQUEST,
> &test_vector);
> - if (test_vector & DPCD_TEST_EDID_READ) {
> + if (test_vector & DP_TEST_LINK_EDID_READ) {
> exynos_dp_write_byte_to_dpcd(dp,
> - DPCD_ADDR_TEST_EDID_CHECKSUM,
> + DP_TEST_EDID_CHECKSUM,
> edid[EDID_CHECKSUM]);
> exynos_dp_write_byte_to_dpcd(dp,
> - DPCD_ADDR_TEST_RESPONSE,
> - DPCD_TEST_EDID_CHECKSUM_WRITE);
> + DP_TEST_RESPONSE,
> + DP_TEST_EDID_CHECKSUM_WRITE);
> }
> }
>
> @@ -193,8 +193,8 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
> int i;
> int retval;
>
> - /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
> - retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_DPCD_REV,
> + /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
> + retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
> 12, buf);
> if (retval)
> return retval;
> @@ -214,14 +214,14 @@ static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
> {
> u8 data;
>
> - exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
> + exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
>
> if (enable)
> - exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
> - DPCD_ENHANCED_FRAME_EN |
> + exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
> + DP_LANE_COUNT_ENHANCED_FRAME_EN |
> DPCD_LANE_COUNT_SET(data));
> else
> - exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
> + exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
> DPCD_LANE_COUNT_SET(data));
> }
>
> @@ -230,7 +230,7 @@ static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
> u8 data;
> int retval;
>
> - exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
> + exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
> retval = DPCD_ENHANCED_FRAME_CAP(data);
>
> return retval;
> @@ -250,8 +250,8 @@ static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
> exynos_dp_set_training_pattern(dp, DP_NONE);
>
> exynos_dp_write_byte_to_dpcd(dp,
> - DPCD_ADDR_TRAINING_PATTERN_SET,
> - DPCD_TRAINING_PATTERN_DISABLED);
> + DP_TRAINING_PATTERN_SET,
> + DP_TRAINING_PATTERN_DISABLE);
> }
>
> static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
> @@ -295,7 +295,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
> /* Setup RX configuration */
> buf[0] = dp->link_train.link_rate;
> buf[1] = dp->link_train.lane_count;
> - retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET,
> + retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
> 2, buf);
> if (retval)
> return retval;
> @@ -322,16 +322,16 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>
> /* Set RX training pattern */
> retval = exynos_dp_write_byte_to_dpcd(dp,
> - DPCD_ADDR_TRAINING_PATTERN_SET,
> - DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1);
> + DP_TRAINING_PATTERN_SET,
> + DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
> if (retval)
> return retval;
>
> for (lane = 0; lane < lane_count; lane++)
> - buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
> - DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
> + buf[lane] = DP_TRAIN_PRE_EMPHASIS_0 |
> + DP_TRAIN_VOLTAGE_SWING_400;
>
> - retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
> + retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
> lane_count, buf);
>
> return retval;
> @@ -352,7 +352,7 @@ static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
>
> for (lane = 0; lane < lane_count; lane++) {
> lane_status = exynos_dp_get_lane_status(link_status, lane);
> - if ((lane_status & DPCD_LANE_CR_DONE) == 0)
> + if ((lane_status & DP_LANE_CR_DONE) == 0)
> return -EINVAL;
> }
> return 0;
> @@ -364,13 +364,13 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
> int lane;
> u8 lane_status;
>
> - if ((link_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
> + if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
> return -EINVAL;
>
> for (lane = 0; lane < lane_count; lane++) {
> lane_status = exynos_dp_get_lane_status(link_status, lane);
> - lane_status &= DPCD_CHANNEL_EQ_BITS;
> - if (lane_status != DPCD_CHANNEL_EQ_BITS)
> + lane_status &= DP_CHANNEL_EQ_BITS;
> + if (lane_status != DP_CHANNEL_EQ_BITS)
> return -EINVAL;
> }
>
> @@ -468,9 +468,9 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
> DPCD_PRE_EMPHASIS_SET(pre_emphasis);
>
> if (voltage_swing == VOLTAGE_LEVEL_3)
> - training_lane |= DPCD_MAX_SWING_REACHED;
> + training_lane |= DP_TRAIN_MAX_SWING_REACHED;
> if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
> - training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
> + training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>
> dp->link_train.training_lane[lane] = training_lane;
> }
> @@ -487,12 +487,12 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
> lane_count = dp->link_train.lane_count;
>
> retval = exynos_dp_read_bytes_from_dpcd(dp,
> - DPCD_ADDR_LANE0_1_STATUS, 2, link_status);
> + DP_LANE0_1_STATUS, 2, link_status);
> if (retval)
> return retval;
>
> retval = exynos_dp_read_bytes_from_dpcd(dp,
> - DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
> + DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
> if (retval)
> return retval;
>
> @@ -501,9 +501,9 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
> exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
>
> retval = exynos_dp_write_byte_to_dpcd(dp,
> - DPCD_ADDR_TRAINING_PATTERN_SET,
> - DPCD_SCRAMBLING_DISABLED |
> - DPCD_TRAINING_PATTERN_2);
> + DP_TRAINING_PATTERN_SET,
> + DP_LINK_SCRAMBLING_DISABLE |
> + DP_TRAINING_PATTERN_2);
> if (retval)
> return retval;
>
> @@ -543,7 +543,7 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
> dp->link_train.training_lane[lane], lane);
>
> retval = exynos_dp_write_bytes_to_dpcd(dp,
> - DPCD_ADDR_TRAINING_LANE0_SET, lane_count,
> + DP_TRAINING_LANE0_SET, lane_count,
> dp->link_train.training_lane);
> if (retval)
> return retval;
> @@ -562,7 +562,7 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
> lane_count = dp->link_train.lane_count;
>
> retval = exynos_dp_read_bytes_from_dpcd(dp,
> - DPCD_ADDR_LANE0_1_STATUS, 2, link_status);
> + DP_LANE0_1_STATUS, 2, link_status);
> if (retval)
> return retval;
>
> @@ -572,12 +572,12 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
> }
>
> retval = exynos_dp_read_bytes_from_dpcd(dp,
> - DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
> + DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
> if (retval)
> return retval;
>
> retval = exynos_dp_read_byte_from_dpcd(dp,
> - DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED, &link_align);
> + DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
> if (retval)
> return retval;
>
> @@ -619,7 +619,7 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
> exynos_dp_set_lane_link_training(dp,
> dp->link_train.training_lane[lane], lane);
>
> - retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
> + retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
> lane_count, dp->link_train.training_lane);
>
> return retval;
> @@ -634,7 +634,7 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
> * For DP rev.1.1, Maximum link rate of Main Link lanes
> * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
> */
> - exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
> + exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
> *bandwidth = data;
> }
>
> @@ -647,7 +647,7 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
> * For DP rev.1.1, Maximum number of Main Link lanes
> * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
> */
> - exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
> + exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
> *lane_count = DPCD_MAX_LANE_COUNT(data);
> }
>
> @@ -819,20 +819,20 @@ static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
> exynos_dp_enable_scrambling(dp);
>
> exynos_dp_read_byte_from_dpcd(dp,
> - DPCD_ADDR_TRAINING_PATTERN_SET,
> + DP_TRAINING_PATTERN_SET,
> &data);
> exynos_dp_write_byte_to_dpcd(dp,
> - DPCD_ADDR_TRAINING_PATTERN_SET,
> - (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
> + DP_TRAINING_PATTERN_SET,
> + (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
> } else {
> exynos_dp_disable_scrambling(dp);
>
> exynos_dp_read_byte_from_dpcd(dp,
> - DPCD_ADDR_TRAINING_PATTERN_SET,
> + DP_TRAINING_PATTERN_SET,
> &data);
> exynos_dp_write_byte_to_dpcd(dp,
> - DPCD_ADDR_TRAINING_PATTERN_SET,
> - (u8)(data | DPCD_SCRAMBLING_DISABLED));
> + DP_TRAINING_PATTERN_SET,
> + (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
> }
> }
>
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
> index d6a900d..6324f51 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.h
> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
> @@ -14,6 +14,7 @@
> #define _EXYNOS_DP_CORE_H
>
> #include <drm/drm_crtc.h>
> +#include <drm/drm_dp_helper.h>
> #include <drm/exynos_drm.h>
>
> #define DP_TIMEOUT_LOOP_COUNT 100
> @@ -261,69 +262,17 @@ void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
> #define EDID_EXTENSION_FLAG 0x7e
> #define EDID_CHECKSUM 0x7f
>
> -/* Definition for DPCD Register */
> -#define DPCD_ADDR_DPCD_REV 0x0000
> -#define DPCD_ADDR_MAX_LINK_RATE 0x0001
> -#define DPCD_ADDR_MAX_LANE_COUNT 0x0002
> -#define DPCD_ADDR_LINK_BW_SET 0x0100
> -#define DPCD_ADDR_LANE_COUNT_SET 0x0101
> -#define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
> -#define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
> -#define DPCD_ADDR_LANE0_1_STATUS 0x0202
> -#define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED 0x0204
> -#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
> -#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
> -#define DPCD_ADDR_TEST_REQUEST 0x0218
> -#define DPCD_ADDR_TEST_RESPONSE 0x0260
> -#define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261
> -#define DPCD_ADDR_SINK_POWER_STATE 0x0600
> -
> -/* DPCD_ADDR_MAX_LANE_COUNT */
> +/* DP_MAX_LANE_COUNT */
> #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
> #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
>
> -/* DPCD_ADDR_LANE_COUNT_SET */
> -#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
> +/* DP_LANE_COUNT_SET */
> #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
>
> -/* DPCD_ADDR_TRAINING_PATTERN_SET */
> -#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
> -#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
> -#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
> -#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
> -#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
> -
> -/* DPCD_ADDR_TRAINING_LANE0_SET */
> -#define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5)
> +/* DP_TRAINING_LANE0_SET */
> #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
> #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
> -#define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3)
> -#define DPCD_MAX_SWING_REACHED (0x1 << 2)
> #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
> #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
> -#define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0)
> -
> -/* DPCD_ADDR_LANE0_1_STATUS */
> -#define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2)
> -#define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1)
> -#define DPCD_LANE_CR_DONE (0x1 << 0)
> -#define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \
> - DPCD_LANE_CHANNEL_EQ_DONE|\
> - DPCD_LANE_SYMBOL_LOCKED)
> -
> -/* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
> -#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
> -#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
> -#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
> -
> -/* DPCD_ADDR_TEST_REQUEST */
> -#define DPCD_TEST_EDID_READ (0x1 << 2)
> -
> -/* DPCD_ADDR_TEST_RESPONSE */
> -#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
> -
> -/* DPCD_ADDR_SINK_POWER_STATE */
> -#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
> -#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
>
> #endif /* _EXYNOS_DP_CORE_H */
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index cfcacec..918a226 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -291,6 +291,8 @@
> # define DP_TEST_NAK (1 << 1)
> # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
>
> +#define DP_TEST_EDID_CHECKSUM 0x261
> +
> #define DP_TEST_SINK 0x270
> #define DP_TEST_SINK_START (1 << 0)
>
> --
> 1.7.10.4
>
>
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