https://bugzilla.kernel.org/show_bug.cgi?id=71891 --- Comment #25 from Christian König <deathsimple@xxxxxxxxxxx> --- Thanks for testing this Dieter, that actually saved me quite some time. The formular for the clock is (fb_div*ref_clock)/(fb_factor*post_div). fb_factor is a fixed value comming from the hardware design (43663) ref_clock (reference clock) is the external input clock to the RV730 asic, it's value is burned into the BIOS (usually 27MHz for R7xx). fb_div and post_div are the values the driver calculates to get a certain frequency for the chip. So for our values here we get: (808574*27MHz)/(43663*5) = ~100MHz (2585818*27MHz)/(43663*3) = ~533MHz (2585818*27MHz)/(43663*4) = ~400MHz Over all that looks perfectly fine. Please provide the content of the registers CG_UPLL_FUNC_CNTL, CG_UPLL_FUNC_CNTL_2 and CG_UPLL_FUNC_CNTL_3. E.g. install radeontool and execute: radeonreg regmatch 0x718 radeonreg regmatch 0x71c radeonreg regmatch 0x720 Thx, Christian. -- You are receiving this mail because: You are watching the assignee of the bug. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
