https://bugzilla.kernel.org/show_bug.cgi?id=71891 --- Comment #21 from Christian König <deathsimple@xxxxxxxxxxx> --- (In reply to sdh from comment #19) > Anything I can do to help debug this? Well, do you have some experience with kernel hacking? The problem is somewhere in rv770_set_uvd_clocks found in the kernel source file drivers/gpu/drm/radeon/rv770.c. Despite the name this function is used for RV710, RV730 (yours) and RV770. The implementation works fine on my RV710, but it looks like on some asics the reference frequency (or something else) is different and so programming the PLL results in a way to high frequency and the whole box becomes completely unstable because of this. A good start would be to get me the values of fb_div, vclk_div and dclk_div used in that function. You could also try to play with the frequencies used for radeon_set_uvd_clocks. Defaults are 533MHz and 400MHz (e.g. radeon_set_uvd_clocks(rdev, 53300, 40000)), but using those seems to make your system unstable. -- You are receiving this mail because: You are watching the assignee of the bug. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
