Hi YoungJun,
Thanks for the whole patchset.
On 04/15/2014 07:47 AM, YoungJun Cho wrote:
> Some phy control registers are not kept after software reset.
> So this patch makes the clocks containing phy control to be set
> after software reset.
>
> Signed-off-by: YoungJun Cho <yj44.cho@xxxxxxxxxxx>
> Signed-off-by: Inki Dae <inki.dae@xxxxxxxxxxx>
> Signed-off-by: Kyungmin Park <kyungmin.park@xxxxxxxxxxx>
> ---
> drivers/gpu/drm/exynos/exynos_drm_dsi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> index 956e5f3..2cf1f0b 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> @@ -946,10 +946,10 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
>
> static int exynos_dsi_init(struct exynos_dsi *dsi)
> {
> - exynos_dsi_enable_clock(dsi);
> exynos_dsi_reset(dsi);
> enable_irq(dsi->irq);
> exynos_dsi_wait_for_reset(dsi);
> + exynos_dsi_enable_clock(dsi);
> exynos_dsi_init_link(dsi);
>
> return 0;
Are you sure this sequence is OK? I have observed that sequence:
dsi power off
dsi power on
dsi_reset
on 4210 or 4412 resulted in lack of irq after reset, only enabling
clocks helped.
And according to documentation reset do not touch registers set by
exynos_dsi_enable_clock,
so the current solution should work.
Regards
Andrzej
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