Hi, Kindly hold the merging of this patch, i shall update it with proper values, once i receive it from our hardware team. Regards, ShirisH S On Thu, Mar 20, 2014 at 1:05 PM, Stéphane Marchesin <stephane.marchesin@xxxxxxxxx> wrote: > > > > On Wed, Mar 12, 2014 at 10:28 PM, Shirish S <s.shirish@xxxxxxxxxxx> wrote: >> >> This patch adds support for the below mentioned >> pixel clocks in Exynos5250. >> Without them, following display modes won't >> be supported: >> >> 71 MHz - 1280x800@60Hz RB >> 73.25 MHz - 800x600@120Hz RB >> 88.75 MHz - 1440x900@60Hz RB >> 115.5 MHz - 1024x768@120Hz RB >> 119 MHz - 1680x1050@60Hz RB >> >> Signed-off-by: Shirish S <s.shirish@xxxxxxxxxxx> >> --- >> V2: Incorporated review comments >> >> drivers/gpu/drm/exynos/exynos_hdmi.c | 45 >> ++++++++++++++++++++++++++++++++++ >> 1 file changed, 45 insertions(+) >> >> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c >> b/drivers/gpu/drm/exynos/exynos_hdmi.c >> index 12fdf55..406d89d 100644 >> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c >> +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c >> @@ -304,6 +304,24 @@ static const struct hdmiphy_config >> hdmiphy_v14_configs[] = { >> }, >> }, >> { >> + .pixel_clock = 71000000, >> + .conf = { >> + 0x01, 0x91, 0x1e, 0x15, 0x40, 0x3c, 0xce, 0x08, >> + 0x04, 0x20, 0xb2, 0xd8, 0x45, 0xa0, 0xac, 0x80, >> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, >> + 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, >> + }, >> + }, >> + { >> + .pixel_clock = 73250000, >> + .conf = { >> + 0x01, 0xd1, 0x1f, 0x15, 0x40, 0x18, 0xe9, 0x08, >> + 0x02, 0xa0, 0xb7, 0xd8, 0x45, 0xa0, 0xac, 0x80, >> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, >> + 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, >> + }, >> + }, >> + { >> .pixel_clock = 74176000, >> .conf = { >> 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08, >> @@ -331,6 +349,15 @@ static const struct hdmiphy_config >> hdmiphy_v14_configs[] = { >> }, >> }, >> { >> + .pixel_clock = 88750000, >> + .conf = { >> + 0x01, 0x91, 0x25, 0x17, 0x40, 0x30, 0xfe, 0x08, >> + 0x06, 0x20, 0xde, 0xd8, 0x45, 0xa0, 0xac, 0x80, >> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, >> + 0x54, 0x8a, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, >> + }, >> + }, >> + { >> .pixel_clock = 106500000, >> .conf = { >> 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08, >> @@ -349,6 +376,24 @@ static const struct hdmiphy_config >> hdmiphy_v14_configs[] = { >> }, >> }, >> { >> + .pixel_clock = 115500000, >> + .conf = { >> + 0x01, 0xd1, 0x30, 0x1a, 0x40, 0x40, 0x10, 0x04, >> + 0x04, 0xa0, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80, >> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, >> + 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, >> + }, >> + }, >> + { >> + .pixel_clock = 119000000, > > > > We have found that the 119MHz clock doesn't work in Chrome OS (the clock > doesn't stabilize), so we removed it. We should probably remove it here as > well. > > Stéphane > I have informed this issue to the hardware team, and will update it once i receive any changes, Also i >> + .conf = { >> + 0x01, 0x91, 0x32, 0x14, 0x40, 0x60, 0xd8, 0x08, >> + 0x06, 0x20, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80, >> + 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, >> + 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, >> + }, >> + }, >> + { >> .pixel_clock = 146250000, >> .conf = { >> 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08, >> -- >> 1.7.10.4 >> >> _______________________________________________ >> dri-devel mailing list >> dri-devel@xxxxxxxxxxxxxxxxxxxxx >> http://lists.freedesktop.org/mailman/listinfo/dri-devel > > _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel