Comment # 44
on bug 76564
from jeroen
(In reply to comment #43) > We could also update the adjusted mode clock to the actual clock set by the > pll so that drm_calc_timestamping_constants() uses the actual clock value on > the PLL. E.g., > > diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c > b/drivers/gpu/drm/radeon/atombios_crtc.c > index daa4dd3..2a2da82 100644 > --- a/drivers/gpu/drm/radeon/atombios_crtc.c > +++ b/drivers/gpu/drm/radeon/atombios_crtc.c > @@ -1085,6 +1085,7 @@ static void atombios_crtc_set_pll(struct drm_crtc > *crtc, struct drm_display_mode > atombios_crtc_program_ss(rdev, ATOM_ENABLE, > radeon_crtc->pll_id, > radeon_crtc->crtc_id, > &radeon_crtc->ss); > } > + mode->clock = pll_clock * 10; > } > > static int dce4_crtc_do_set_base(struct drm_crtc *crtc, I think that would only help if radeon_compute_pll_avivo could not compute an exact match. In the case of 23.976Hz the target clock is 74170kHz and the PLL is set exactly to this value. This does raise another question why the target clock' last digit is always zero? For example, for 23.976Hz the target clock should be 74176kHz (with correct rounding). I looked through the source code, but the target clock seems to come all the way from some deep generic drm code. 74176kHz could be matched by the PLL using fb=927.2, post_div=10 and ref_div=125
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