Comment # 33
on bug 76564
from jeroen
The PLL struct values are on my system: pll_in_min=675, pll_in_max=5000, pll_out_min=64800, pll_out_max=120000, lcd_pll_out_min=0, lcd_pll_out_max=120000, min_ref_div=2, max_ref_div=1023, min_post_div=2, max_post_div=127, min_feedback_div=4, max_feedback_div=2047, min_frac_feedback_div=0, max_frac_feedback_div=9, best_vco=0, reference_freq=10000, reference_div=0, post_div=0, flags=1040 I guess this means that for 148.5MHz the post_div has to be 5,6,7 or 8? Also if I understand the code correctly the ref_div is always 2 as the fb fraction is used?
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